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參數(shù)資料
| 型號： | AD5325BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 2WIRE I2C 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 125k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
AD5305/AD5315/AD5325
Rev. G | Page 21 of 24
AD5305/AD5315/AD5325 AS A DIGITALLY
PROGRAMMABLE WINDOW DETECTOR
A digitally programmable upper/lower limit detector using two
of the DACs in the AD5305/AD5315/AD5325 is shown in
Figure 39. The upper and lower limits for the test are loaded to
DAC A and DAC B, which, in turn, set the limits on the CMP04. If
the signal at the VIN input is not within the programmed window,
an LED indicates the fail condition. Similarly, DAC C and DAC D
can be used for window detection on a second VIN signal.
5V
GND
REFIN
1/6 74HC05
FAIL
PASS
1k
SCL
SDA
SCL
DIN
1k
1ADDITIONAL PINS OMITTED FOR CLARITY.
0.1F
10F
VREF
1/2
AD5305/
AD5315/
AD53251
VOUTA
VOUTB
VDD
VIN
1/2
CMP04
PASS/FAIL
009
30-
039
Figure 39. Window Detection
COARSE AND FINE ADJUSTMENT USING THE
AD5305/AD5315/AD5325
Two of the DACs in the AD5305/AD5315/AD5325 can be paired
together to form a coarse and fine adjustment function, as shown
in Figure 40. DAC A is used to provide the coarse adjustment
while DAC B provides the fine adjustment. Varying the ratio of
R1 and R2 changes the relative effect of the coarse and fine
adjustments. With the resistor values and external reference shown
in Figure 40, the output amplifier has unity gain for the DAC A
output. As a result, the output range is 0 V to 2.5 V 1 LSB. For
DAC B, the amplifier has a gain of 7.6 × 103, giving DAC B a
range equal to 19 mV. Similarly, DAC C and DAC D can be
paired together for coarse and fine adjustment.
The circuit is shown with a 2.5 V reference, but reference
voltages up to VDD can be used. The op amps indicated allows
a rail-to-rail output swing.
1F
REFIN
GND
0.1F
10F
GND
5V
VOUT
1ADDITIONAL PINS OMITTED FOR CLARITY.
R3
51.2k
R4
390
R1
390
R2
51.2k
AD820/
OP295
VDD = 5V
VDD
VOUTA
VOUTB
1/2
AD5305/
AD5315/
AD53251
AD780/REF192
WITH VDD = 5V
VOUT
VIN
EXT
REF
00
930
-04
0
Figure 40. Coarse/Fine Adjustment
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD5305/AD5315/AD5325 is mounted
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. If the
AD5305/AD5315/AD5325 is in a system where multiple devices
require an AGND-to-DGND connection, the connection
should be made at one point only. The star ground point should
be established as close as possible to the device. The AD5305/
AD5315/AD5325 should have ample supply bypassing of 10 μF
in parallel with 0.1 μF on the supply located as close to the
package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
The power supply lines of the AD5305/AD5315/AD5325
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply
line. Fast switching signals such as clocks should be shielded
with digital ground to avoid radiating noise to other parts of the
board, and should never be run near the reference inputs. A
ground line routed between the SDA and SCL lines helps reduce
crosstalk between them (not required on a multilayer board as
there is a separate ground plane, but separating the lines does help).
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best, but is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to ground plane
while signal traces are placed on the solder side.
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| AD5325BRMZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 500 ??A, 2-Wire Interface Interface |
| AD5325BRMZ-REEL | 功能描述:IC DAC 12BIT 2WIRE I2C 10MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5325BRMZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 500 ??A, 2-Wire Interface Interface |
| AD5325BRMZ-REEL7 | 功能描述:IC DAC 12BIT 2WIRE I2C 10MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5325BRMZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 500 ??A, 2-Wire Interface Interface |
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