參數(shù)資料
型號: AD5330BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 14/28頁
文件大小: 0K
描述: IC DAC 8BIT SNGL VOUT 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 75
設(shè)置時(shí)間: 6µs
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1.25mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 167k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 21 of 28
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUITS
The AD5330/AD5331/AD5340/AD5341 can be used with
a wide range of reference voltages, especially if the reference
inputs are configured to be unbuffered, in which case the
devices offer full, one-quadrant multiplying capability over a
reference range of 0.25 V to VDD. More typically, these devices
can be used with a fixed, precision reference voltage. Figure 43
shows a typical setup for the devices when using an external
reference connected to the unbuffered reference inputs. If the
reference inputs are unbuffered, the reference input range is
from 0.25 V to VDD, but if the on-chip reference buffers are
used, the reference range is reduced. Suitable references for 5 V
operation are the AD780 and REF192. For 2.5 V operation, a
suitable external reference is the AD589, a 1.23 V band gap
reference.
AD5330/AD5331/
AD5340/AD5341
VOUT
VDD = 2.5V TO 5.5V
VDD
GND
VREF
GND
EXT
REF
+
0.1F
10F
VOUT
VIN
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 2.5V
06
85
2-
044
Figure 43. AD5330/AD5331/AD5340/AD5341 Using External Reference
DRIVING VDD FROM THE REFERENCE VOLTAGE
If an output range of 0 V to VDD is required, the simplest
solution is to connect the reference inputs to VDD. Because this
supply may not be very accurate and may be noisy, the devices
can be powered from the reference voltage, for example using
a 5 V reference such as the ADP667, as shown in Figure 44.
AD5330/AD5331/
AD5340/AD5341
GND SHDN
VOUT
ADP667
VSET
6V TO 16V
VOUT
VDD
VIN
GND
VREF
+
0.1F
10F
06
85
2-
0
45
Figure 44. Using an ADP667 as Power and Reference to
AD5330/AD5331/AD5340/AD5341
BIPOLAR OPERATION USING THE AD5330/AD5331/
AD5340/AD5341
The AD5330/AD5331/AD5340/AD5341 are designed for
single-supply operation, but bipolar operation is achievable
using the circuit shown in Figure 45. The circuit shown has
been configured to achieve an output voltage range of –5 V <
VO < +5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or OP295 as the output amplifier.
The output voltage for any input code can be calculated as follows:
VO
= [(1 + R4/R3) × (R2/(R1 + R2) × (2 × VREF × D/2N)] –
R4
× VREF/R3
where:
D
is the decimal equivalent of the code loaded to the DAC.
N
is the DAC resolution.
VREF
is the reference voltage input.
with:
VREF = 2.5 V.
R1 = R3 = 10 kΩ.
R2 = R4 = 20 kΩ and VDD = 5 V.
VO = (10 × D/2N) 5.
VDD = 5V
+
0.1F
10F
R2
20k
R1
10k
R3
10k
R4
20k
GND
VO = ±5V
+5V
–5V
AD5330/AD5331/
AD5340/AD5341
VREF
VOUT
VDD
GND
EXT
REF
VOUT
VIN
AD780/REF192
WITH VDD = 5V
OR
AD589 WITH VDD = 2.5V
0.1F
068
52
-0
46
Figure 45. Bipolar Operation using the AD5330/AD5331/AD5340/AD5341
DECODING MULTIPLE AD5330/AD5331/
AD5340/AD5341
The CS pin on these devices can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same data and WR pulses, but only CS to one
of the DACs is active at any one time, so data is only written to
the DAC whose CS is low. If multiple AD5341s are being used, a
common HBEN line is also required to determine if the data is
written to the high byte or low byte register of the selected DAC.
The 74HC139 is used as a 2-line to 4-line decoder to address
any of the DACs in the system. To prevent timing errors, the
enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 46 shows a
diagram of a typical setup for decoding multiple devices in a
system. Once data has been written sequentially to all DACs in
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