TA = 25°C 200 100 0 2.5 3" />
參數(shù)資料
型號: AD5330BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 7/28頁
文件大?。?/td> 0K
描述: IC DAC 8BIT SNGL VOUT 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 75
設(shè)置時間: 6µs
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1.25mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 167k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 15 of 28
300
TA = 25°C
200
100
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
I DD
(
A
)
VDD (V)
06
85
2-
02
7
Figure 26. Supply Current vs. Supply Voltage
0.5
TA = 25°C
0
0.1
0.2
0.3
0.4
2.5
3.0
3.5
4.0
4.5
5.0
5.5
I DD
(
A
)
VDD (V)
06
85
2-
02
8
Figure 27. Power-Down Current vs. Supply Voltage
I DD
(
A
)
VLOGIC (V)
1800
TA = 25°C
0
200
400
600
800
1000
1200
1400
1600
01
2345
VDD = 5V
VDD = 3V
06
85
2-
02
9
Figure 28. Supply Current vs. Logic Input Voltage
CLK
CH1
1V
CH2
5V
TA = 25°C
VDD = 5V
VOUT
TIME BASE = 5s/DIV
06
85
2-
03
0
Figure 29. Half-Scale Settling ( to Scale Code Change)
CH1
2V
CH2
200mV
TIME BASE = 200s/DIV
TA = 25°C
VDD = 5V
VREF = 2V
VDD
VOUTA
06
85
2-
03
1
Figure 30. Power-On Reset to 0 V
CH1
500mV
CH2
5V
TIME BASE = 1s/DIV
TA = 25°C
VDD = 5V
VREF = 2V
VOUTA
PD
06
85
2-
0
32
Figure 31. Exiting Power-Down to Midscale
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