參數(shù)資料
型號： AD5338BRMZ-1
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 2.5 V to 5.5 V, 250 UA, 2-Wire Interface Dual-Voltage Output, 8-/10-/12-Bit DACs
中文描述： SERIAL INPUT LOADING, 7 us SETTLING TIME, 10-BIT DAC, PDSO8
封裝： ROHS COMPLIANT, MO-187AA, MSOP-8
文件頁數(shù)： 6/24頁
文件大小： 654K
代理商： AD5338BRMZ-1
AD5337/AD5338/AD5339
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Limit at T
MIN
, T
MAX
(A and B Versions)
f
SCL
400
t
1
2.5
t
2
0.6
t
3
1.3
t
4
0.6
t
5
100
t
61
0.9
0
t
7
0.6
t
8
0.6
t
9
1.3
t
10
300
0
t
11
250
0
300
20 + 0.1 C
B2
C
B
400
Rev. A | Page 6 of 24
Parameter
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Conditions/Comments
SCL clock frequency
SCL cycle time
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
HD,
STA
, start/repeated start condition hold time
t
SU,
DAT
, data setup time
t
HD,
DAT
, data hold time
t
HD,
DAT
, data hold time
t
SU,
STA
, setup time for repeated start
t
SU,
STO
, stop condition setup time
t
BUF
, bus free time between a stop and a start condition
t
R
, rise time of SCL and SDA when receiving
t
R
, rise time of SCL and SDA when receiving (CMOS-compatible)
t
F
, fall time of SDA when transmitting
t
F
, fall time of SDA when receiving (CMOS-compatible)
t
F
, fall time of SCL and SDA when receiving
t
F
, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
IH
min of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
2
C
B
is the total capacitance of one bus line in pF; t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
STOP
SCL
SDA
START
CONDITION
t
9
t
3
t
4
t
6
t
2
t
5
t
7
t
8
t
1
t
4
t
11
t
10
REPEATED
START
CONDITION
CONDITION
0
Figure 2. 2-Wire Serial Interface Timing Diagram
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