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參數資料
| 型號： | AD5340BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SNGL VOUT 24-TSSOP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 1,000 |
| 設置時間： | 8µs |
| 位數： | 12 |
| 數據接口： | 并聯(lián) |
| 轉換器數目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.25mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 125k |
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AD5330/AD5331/AD5340/AD5341
Rev. A | Page 17 of 28
THEORY OF OPERATION
The AD5330/AD5331/AD5340/AD5341 are single resistor-
string DACs fabricated on a CMOS process with resolutions
of 8, 10, and 12 bits, respectively. They are written to using a
parallel interface. They operate from single supplies of 2.5 V to
5.5 V and the output buffer amplifiers offer rail-to-rail output
swing. The AD5330, AD5340, and AD5341 have a reference
input that can be buffered to draw virtually no current from
the reference source. The reference input of the AD5331 is
unbuffered. The devices have a power-down feature that
reduces current consumption to only 80 nA @ 3 V.
DIGITAL-TO-ANALOG SECTION
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 36 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
Gain
D
V
N
REF
OUT
×
=
2
where:
D
is the decimal equivalent of the binary code, which is loaded
to the DAC register:
0 to 255 for AD5330 (8 Bits)
0 to 1023 for AD5331 (10 Bits)
0 to 4095 for AD5340/AD5341 (12 Bits)
N
is the DAC resolution.
Gain
is the output amplifier gain (1 or 2).
GAIN
VREF
VOUT
BUF
DAC
REGISTER
INPUT
REGISTER
RESISTOR
STRING
OUTPUT
BUFFER AMPLIFIER
REFERENCE
BUFFER
06
85
2-
0
37
Figure 36. Single DAC Channel Architecture
RESISTOR STRING
The resistor-string section is shown in Figure 37. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
TO OUTPUT
AMPLIFIER
R
VREF
06
85
2-
0
38
Figure 37. Resistor String
DAC REFERENCE INPUT
There is a reference input pin for the DAC. The reference
input is buffered on the AD5330, AD5340, and AD5341 but
can be configured as unbuffered also. The reference input of
the AD5331 is unbuffered. The buffered/unbuffered option is
controlled by the BUF pin.
In buffered mode (BUF = 1), the current drawn from an
external reference voltage is virtually zero because the
impedance is at least 10 MΩ. The reference input range is
1 V to 5 V with a 5 V supply.
In unbuffered mode (BUF = 0), the user can have a reference
voltage as low as 0.25 V and as high as VDD because there is no
restriction due to headroom and footroom of the reference
amplifier. The impedance is still large at typically 180 kΩ for
0 V to VREF mode and 90 kΩ for 0 V to 2 × VREF mode. If there is
an external buffered reference (for example, REF192), there is
no need to use the on-chip buffer.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on VREF, GAIN, the load on VOUT, and offset error.
If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V
to VREF.
If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 × VREF. However, because of clamping, the maximum
output is limited to VDD – 0.001 V.
The output amplifier is capable of driving a load of 2 kΩ to
GND or 2 kΩ to VDD in parallel with 500 pF to GND or 500 pF
to VDD. The source and sink capabilities of the output amplifier
can be seen in Figure 24.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at eight bits) of 6 μs with the output unloaded (see
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD5340BRUZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 115 ??A, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs |
| AD5341 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, 500 uA, Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs |
| AD5341BRU | 制造商:Analog Devices 功能描述:DAC 1-CH Resistor-String 12-bit 20-Pin TSSOP 制造商:Analog Devices 功能描述:IC 12BIT DAC SMD 5341 TSSOP20 |
| AD5341BRU-REEL | 制造商:Analog Devices 功能描述:DAC 1-CH Resistor-String 12-bit 20-Pin TSSOP T/R |
| AD5341BRU-REEL7 | 制造商:Analog Devices 功能描述:DAC 1-CH Resistor-String 12-bit 20-Pin TSSOP T/R |
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