參數(shù)資料
型號: AD5360BSTZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 4/29頁
文件大小: 0K
描述: IC DAC 16BIT 16CH SERIAL 52-LQFP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計資源: Automated Calibration Technique That Reduces AD5360 Offset Voltage to Less Than 1 mV (CN0123)
16 Channels of Programmable Output Span Using AD5360 (CN0131)
標準包裝: 1,500
設(shè)置時間: 20µs
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 16
電壓電源: 雙 ±
功率耗散(最大): 245mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應(yīng)商設(shè)備封裝: 52-LQFP(10x10)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 16 電壓,單極;16 電壓,雙極
采樣率(每秒): *
配用: EVAL-AD5360EBZ-ND - BOARD EVAL FOR AD5360
AD5360/AD5361
Rev. A | Page 11 of 28
Pin No.
Mnemonic
Description
LQFP
LFCSP
38
40
SIGGND0
Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to
this voltage.
43, 51
45, 53
DGND
Ground for All Digital Circuitry. Both DGND pins should be connected to the
DGND plane.
44, 50
46, 52
DVCC
Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1
μF ceramic capacitors and 10 μF capacitors.
45
47
SYNC
Active Low or SYNC Input for SPI Interface. This is the frame synchronization
signal for the SPI serial interface. See
,
, and the
section for more details.
46
48
SCLK
Serial Clock Input for SPI Interface. See Figure 4, Figure 5, and the Serial
Interface section for more details.
47
49
SDI
Serial Data Input for SPI Interface. See Figure 4, Figure 5, and the Serial
Interface section for more details.
48
50
PEC
Packet Error Check Output. This is an open-drain output with a 50 kΩ pull-up
that goes low if the packet error check fails.
49
51
SDO
Serial Data Output for SPI Interface. See Figure 4, Figure 5, and the Serial
Interface section for more details.
52
54
AGND
Ground for All Analog Circuitry. The AGND pin should be connected to the
AGND plane.
EP
Connect to VSS
Exposed Paddle.
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