參數(shù)資料
型號: AD5360BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 26/29頁
文件大?。?/td> 0K
描述: IC DAC 16BIT 16CH SERIAL 52-LQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計資源: Automated Calibration Technique That Reduces AD5360 Offset Voltage to Less Than 1 mV (CN0123)
16 Channels of Programmable Output Span Using AD5360 (CN0131)
標準包裝: 1
設(shè)置時間: 20µs
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 16
電壓電源: 雙 ±
功率耗散(最大): 245mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應(yīng)商設(shè)備封裝: 52-LQFP(10x10)
包裝: 托盤
輸出數(shù)目和類型: 16 電壓,單極;16 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
配用: EVAL-AD5360EBZ-ND - BOARD EVAL FOR AD5360
AD5360/AD5361
Rev. A | Page 5 of 28
Parameter
B Version1
Unit
Test Conditions/Comments
DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC)
Output Low Voltage
0.5
V max
Sinking 200 μA
Output High Voltage (SDO)
DVCC 0.5
V min
Sourcing 200 μA
High Impedance Leakage Current
±5
μA max
SDO only
High Impedance Output Capacitance4
10
pF typ
TEMPERATURE SENSOR (TEMP_OUT)4
Accuracy
±1
°C typ
@ 25°C
±5
°C typ
40°C < T < +85°C
Output Voltage at 25°C
1.46
V typ
Output Voltage Scale Factor
4.4
mV/°C typ
Output Load Current
200
μA max
Current source only
Power-On Time
10
ms typ
To within ±5°C
POWER REQUIREMENTS
DVCC
2.5/5.5
V min/max
VDD
8/16.5
V min/max
VSS
4.5/16.5
V min/max
Power Supply Sensitivity4
Full Scale/ VDD
75
dB typ
Full Scale/ VSS
75
dB typ
Full Scale/ DVCC
90
dB typ
DICC
2
mA max
VCC = 5.5 V, VIH = DVCC, VIL = GND
IDD
10
mA max
Outputs unloaded
ISS
10
mA max
Outputs unloaded
Power-Down Mode
Bit 0 in the Control Register is 1
DICC
5
μA typ
IDD
35
μA typ
ISS
35
μA typ
Power Dissipation
Power Dissipation Unloaded (P)
245
mW max
VSS = 12 V, VDD = +12 V, DVCC = 2.5 V
Junction Temperature
130
°C max
TJ = TA + PTOTAL × θJA
1 Temperature range for B version: 40°C to +85°C. Typical specifications are at 25°C.
2 Specifications are guaranteed for a 5 V reference only.
3 VOUTx refers to any of VOUT0 to VOUT15.
4 Guaranteed by design and characterization, not production tested.
AC CHARACTERISTICS
DVCC = 2.5 V; VDD = 15 V; VSS = 15 V; VREF = 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M), offset (C), and
DAC offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
20
μs typ
Full-scale change
30
μs max
DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate
1
V/μs typ
Digital-to-Analog Glitch Energy
5
nV-s typ
Glitch Impulse Peak Amplitude
10
mV max
Channel-to-Channel Isolation
100
dB typ
VREF0, VREF1 = 2 V p-p, 1 kHz
DAC-to-DAC Crosstalk
10
nV-s typ
Digital Crosstalk
0.2
nV-s typ
Digital Feedthrough
0.02
nV-s typ
Effect of input bus activity on DAC output under test
Output Noise Spectral Density @ 10 kHz
250
nV/√Hz typ
VREF0 = VREF1 = 0 V
1 Guaranteed by design and characterization, not production tested.
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