參數(shù)資料
型號(hào)： AD5360BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 3/29頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT 16CH SERIAL 52-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Automated Calibration Technique That Reduces AD5360 Offset Voltage to Less Than 1 mV (CN0123)
16 Channels of Programmable Output Span Using AD5360 (CN0131)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 20µs
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 16
電壓電源： 雙 ±
功率耗散（最大）： 245mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 52-LQFP
供應(yīng)商設(shè)備封裝： 52-LQFP（10x10）
包裝： 托盤(pán)
輸出數(shù)目和類型： 16 電壓，單極；16 電壓，雙極
采樣率（每秒）： *
產(chǎn)品目錄頁(yè)面： 782 (CN2011-ZH PDF)
配用： EVAL-AD5360EBZ-ND - BOARD EVAL FOR AD5360
AD5360/AD5361
Rev. A | Page 10 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05
76
1-
0
22
52 51 50 49 48
43 42 41 40
47 46 45 44
14 15 16 17 18 19 20 21 22 23 24 25 26
1
2
3
4
5
6
7
8
9
10
11
13
12
39
38
37
36
35
34
33
32
31
30
29
28
27
NC
VO
U
T
8
VO
U
T
9
VO
U
T
10
VO
U
T
11
S
IG
G
ND1
VO
U
T
12
VO
U
T
13
VO
U
T
14
VO
U
T
15
NC
LDAC
CLR
RESET
BIN/2SCOMP
BUSY
GPIO
MON_OUT
MON_IN0
NC
VDD
VSS
VREF1
VOUT4
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
TEMP_OUT
MON_IN1
VREF0
NC
VSS
VDD
NC
NC = NO CONNECT
AG
ND
DV
CC
SD
O
PEC
SD
I
SC
L
K
SYN
C
DV
CC
DG
ND
VO
U
T
7
VO
U
T
6
VO
U
T
5
DG
ND
AD5360/
AD5361
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
PIN 1
INDICATOR
NC = NO CONNECT
1
RESET
2
BIN/2SCOMP
3
BUSY
4
GPIO
5
MON_OUT
6
MON_IN0
7
NC
8
NC
9
NC
10
NC
11
NC
12
VDD
13
VSS
14
VREF1
35
TEMP_OUT
36
VOUT0
37
VOUT1
38
VOUT2
39
VOUT3
40
SIGGND0
41
VOUT4
42
VOUT5
34
MON_IN1
33
VREF0
32
NC
31
NC
30
VSS
29
VDD
15
N
C
16
N
C
17
V
O
U
T
8
19
V
O
U
T
10
21
S
IG
G
N
D
1
20
V
O
U
T
11
22
V
O
U
T
12
23
V
O
U
T
13
24
V
O
U
T
14
25
V
O
U
T
15
26
N
C
27
N
C
28
N
C
18
V
O
U
T
9
45
D
G
N
D
46
D
V
C
47
S
Y
N
C
48
S
C
L
K
49
S
D
I
50
P
E
C
51
S
D
O
52
D
V
C
53
D
G
N
D
54
A
G
N
D
44
V
O
U
T
7
43
V
O
U
T
6
TOP VIEW
(Not to Scale)
AD5360/
AD5361
55
L
D
A
C
56
C
L
R
0
57
61
-02
8
Figure 7. 52-Lead LQFP Pin Configuration
Figure 8. 56-Lead LFCSP Pin Configuration
Table 5. LQFP Pin Function Descriptions
Pin No.
Mnemonic
Description
LQFP
LFCSP
1
55
LDAC
Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions
section for more information.
2
56
CLR
Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear
Function section for more information.
3
1
RESET
Digital Reset Input.
4
2
BIN/2SCOMP
Data Format Digital Input. Connecting this pin to DGND selects offset binary.
Connecting this pin to logic 1 selects twos complement. This input has a weak
pull-down.
5
3
BUSY
Digital Input/Open-Drain Output. BUSY is open drain when it is an output.
See the BUSY and LDAC Functions section for more information.
6
4
GPIO
Digital I/O Pin. This pin can be configured as an input or output that can be
read or programmed high or low via the serial interface. When configured as
an input, it has a weak pull-down.
7
5
MON_OUT
Analog Multiplexer Output. Any DAC output, the MON_IN0 input, or the
MON_IN1 input can be switched to this output.
8, 32
6, 34
MON_IN0, MON_IN1
Analog Multiplexer Inputs. Can be switched to MON_OUT.
9, 10, 14, 24, 25,
26, 27, 30
7 to 11, 15, 16,
26 to 28, 31, 32
NC
No Connect.
11, 28
12, 29
VDD
Positive Analog Power Supply; +9 V to +16.5 V for specified performance.
These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF
capacitors.
12, 29
13, 30
VSS
Negative Analog Power Supply; 16.5 V to 8 V for specified performance.
These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF
capacitors.
13
14
VREF1
Reference Input for DAC 8 to DAC 15. This voltage is referred to AGND.
19
21
SIGGND1
Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to
this voltage.
31
33
VREF0
Reference Input for DAC 0 to DAC 7. This voltage is referred to AGND.
33
35
TEMP_OUT
Provides an output voltage proportional to chip temperature. This is typically
1.46 V at 25°C with an output variation of 4.4 mV/°C.
34 to 37, 39 to
42, 15 to 18, 20
to 23
36 to 39, 41 to
44, 17 to 20, 22
to 25
VOUT0 to VOUT15
DAC Outputs. Buffered analog outputs for each of the 16 DAC channels. Each
analog output is capable of driving an output load of 10 kΩ to ground.
Typical output impedance of these amplifiers is 0.5 Ω.
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