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參數(shù)資料
| 型號： | AD5384BBC-5REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 40CH 5V 100-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5384 Models Discontinuation 15/May/2012 |
| 標(biāo)準(zhǔn)包裝： | 400 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 80mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 40 電壓，單極 |
| 采樣率（每秒）： | 125k |
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Data Sheet
AD5384
Daisy-Chain Mode
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode is useful in system diagnostics and in reducing the
number of serial interface lines.
Connect the DCEN (daisy-chain enable) pin high, to enable
daisy-chain mode. The first falling edge of SYNC starts the
write cycle. The SCLK is applied continuously to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO
of the first device to the DIN input on the next device in the
chain, a multidevice interface is constructed. Each device in the
system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24N, where N is the total number of
AD5384 devices in the chain.
When the serial transfer to all devices is complete, SYNC goes
high, latches the input data in each device in the daisy-chain,
and prevents any further data from clocking into the input shift
register.
If SYNC is taken high before 24 clocks are clocked into the
device, it is considered a bad frame, and the data is discarded.
The serial clock is either a continuous or a gated clock. A
continuous SCLK source is used only if SYNC is held low for
the correct number of clock cycles. In gated clock mode, use a
burst clock containing the exact number of clock cycles and
take SYNC high after the final clock to latch the data.
Readback Mode
Readback mode is invoked by setting the R/W bit = 1 in the
serial input register write. With R/W = 1, Bits A5 to A0, in
association with Bit REG1 and Bit REG0, select the register to
be read. The remaining data bits in the write sequence are don’t
cares. During the next SPI write, the data appearing on the SDO
output contains the data from the previously addressed register.
For a read of a single register, use the NOP command to clock
out the data from the selected register on SDO. Figure 26 shows
the readback sequence.
For example, to read back the m register of Channel 0 on the
AD5384, the following sequence must be followed. First, write
0x404XXX to the AD5384 input register. This configures the
AD5384 for read mode with the m register of Channel 0
selected. Note that Data Bit DB13 to Data Bit DB0 are don’t
cares. Follow this with a second write, an NOP condition,
0x000000. During this write, the data from the m register clocks
out on the SDO line; data clocked out contains the data from
the m register in Bit DB13 to Bit DB0, and the top 10 bits
contain the address information as previously written. In
readback mode, the SYNC signal frames the data. Data clocks
out on the rising edge of SCLK and is valid on the falling edge
of the SCLK signal. If the SCLK idles high between the write
and read operations of a readback operation, the first bit of data
clocks out on the falling edge of SYNC.
24
48
SCLK
SYNC
DIN
SDO
UNDEFINED
SELECTED REGISTER DATA CLOCKED OUT
NOP CONDITION
INPUT WORD SPECIFIES REGISTER TO BE READ
DB23
DB0
DB23
DB0
DB23
04652-
028
Figure 26. Serial Readback Operation
Rev. B | Page 25 of 32
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