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參數(shù)資料
| 型號： | AD5390BCPZ-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/44頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 16CHAN 5V 64LFCSP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5390/1/2 Redesign Change 16/May/2012 |
| 設計資源： | 8 to 16 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5390/1/2 (CN0029) AD5390/91/92 Channel Monitor Function (CN0030) |
| 標準包裝： | 1 |
| 設置時間： | 8µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 16 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 35mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 16 電壓，單極 |
| 采樣率（每秒）： | 125k |
| 配用： | EVAL-AD5390EBZ-ND - BOARD EVALUATION FOR AD5390 |
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Data Sheet
AD5390/AD5391/AD5392
Rev. E | Page 31 of 44
AD539x ON-CHIP SPECIAL FUNCTION REGISTERS
The AD539x family of parts contains a number of special
function registers (SFRs) as shown in Table 22. SFRs are
addressed with REG1 = 0 and REG0 = 0 and are decoded
using Address Bit A3 to Bit A0.
Table 22. SFR Register Functions (REG1 = 0, REG0 = 0)
R/ W
A3
A2
A1
A0
Function
X
0
NOP (no operation)
0
1
Write CLR code
0
1
0
Soft CLR
0
1
0
Soft power-down
0
1
0
1
Soft power-up
0
1
0
Control register write
1
0
Control register read
0
1
0
1
0
Monitor channel
0
1
Soft reset
SFR Commands
NOP (No Operation)
REG1 = REG0 = 0, A3 to A0 = 0000
Performs no operation, but is useful in readback mode to clock
out data on SDO for diagnostic purposes. BUSY outputs a low
during a NOP operation.
Write CLR Code
REG1 = REG0 = 0, A3 to A0 = 0001
DB13 to DB0 = Contain the CLR data
Bringing the CLR line low or exercising the soft clear function
loads the contents of the DAC registers with the data contained
in the user-configurable CLR register and sets VOUT 0 to
VOUT 15, accordingly. This can be very useful not only for
setting up a specific output voltage in a clear condition but for
calibration purposes. For calibration, the user can load full scale
or zero scale to the clear code register and then issue a hardware
or software clear to load this code to all DACs, removing the
need for individual writes to all DACs. Default on power-up
is all zeros.
Soft CLR
REG1 = REG0 = 0, A3 to A0 = 0010
DB13 to DB0 = Don’t Care
Executing this instruction performs the CLR, which is
functionally the same as that provided by the external CLR pin.
The DAC outputs are loaded with the data in the CLR code
register. The time taken to execute fully the SOFT CLR is
20 s on the AD5390/AD5391 and 15 s on the AD5392. It
is indicated by the BUSY low time.
Soft Power-Down
REG1 = REG0 = 0, A3 to A0 = 1000
DB13 to DB0 = Don’t Care
Executing this instruction performs a global power-down,
which puts all channels into a low power mode, reducing analog
current to 1 A maximum and digital power consumption to
20 A maximum. In power-down mode, the output amplifier
can be configured as a high impedance output or can provide a
100 k load to ground. The contents of all internal registers are
retained in power-down mode.
Soft Power-Up
REG1 = REG0 = 0, A3 to A0 =1001
DB13 to DB0 = Don’t Care
This instruction is used to power up the output amplifiers and
the internal references. The time to exit power-down mode is
8 s. The hardware power-down and software functions are
internally combined in a digital OR function.
Soft Reset
REG1 = REG0 = 0, A5 to A0 = 001111
DB13 to DB0 = Don’t Care
This instruction is used to implement a software reset. All
internal registers are reset to their default values, which
correspond to m at full scale and c at zero scale. The contents
of the DAC registers are cleared, setting all analog outputs to
0 V. The soft reset activation time is 135 s maximum.
Monitor Channel
REG1 = REG0 = 0, A3 to A0 = 01010
DB13 to DB8 = Contain data to address the channel to be
monitored
A monitor function is provided on all devices. This feature,
consisting of a multiplexer addressed via the interface, allows
any channel output to be routed to the MON_OUT pin for
monitoring using an external ADC. In addition to monitoring
all output channels, two external inputs are also provided,
allowing the user to monitor signals external to the AD539x.
The channel monitor function must be enabled in the control
register before any channels are routed to the MON_OUT pin.
On the AD5390 and AD5392 14-bit parts, DB13 to DB8 contain
the channel address for the monitored channel. On the AD5391
12-bit part, DB11 to DB6 contain the channel address for the
channel to be monitored. Selecting Address 63 three-states the
MON_OUT pin.
The channel monitor decoding for the AD5390/AD5392 is
shown in Table 23 and the monitor decoding for the AD5391 is
shown in Table 24.
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