Dual 12-Bit, High Bandwidth, Multiplying DAC with
4-Quadrant Resistors and Parallel Interface
AD5405
Rev. B
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FEATURES
10 MHz multiplying bandwidth
On-chip 4-quadrant resistors allow flexible output ranges
INL of ±1 LSB
40-lead LFCSP package
2.5 V to 5.5 V supply operation
±10 V reference input
21.3 MSPS update rate
Extended temperature range: 40°C to 125°C
4-quadrant multiplication
Power-on reset
0.5 μA typical current consumption
Guaranteed monotonic
Readback function
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION
The AD5405
1 is a CMOS, 12-bit, dual-channel, current output
digital-to-analog converter (DAC). This device operates from a
2.5 V to 5.5 V power supply, making it suited to battery-powered
and other applications.
As a result of manufacture with a CMOS submicron process, the
device offers excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor (RFB)
provides temperature tracking and full-scale voltage output when
combined with an external I-to-V precision amplifier. This device
also contains the 4-quadrant resistors necessary for bipolar
operation and other configuration modes.
This DAC uses data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with 0s, and the DAC
outputs are at zero scale.
The AD5405 has a 6 mm × 6 mm, 40-lead LFCSP package.
1 U.S. Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
VREFA
AD5405
VREFB
VDD
DB0
DB11
DATA
INPUTS
DAC A/B
CS
R/W
GND
CONTROL
LOGIC
INPUT
BUFFER
LATCH
IOUT1B
IOUT1A
12-BIT
R-2R DAC A
RFBA
POWER-ON
RESET
12-BIT
R-2R DAC B
LATCH
R1
2R
R1A
R2
2R
R3
2R
R3A
R2A
R2_3A
R2
2R
R3
2R
R3B
R2B
R2_3B
RFB
2R
R1
2R
RFB
2R
R1B
IOUT2A
IOUT2B
LDAC
0
4463
-0
01
CLR
RFBB
Figure 1.