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參數(shù)資料
| 型號： | AD5405YCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC DUAL 12BIT MULT 40LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 設(shè)置時間： | 80ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 21.3M |
| 配用： | EVAL-AD5405EB-ND - BOARD EVAL FOR AD5405 |
AD5405
Rev. B | Page 14 of 24
GENERAL DESCRIPTION
DAC SECTION
The AD5405 is a 12-bit, dual-channel, current-output DAC
consisting of a standard inverting R-2R ladder configuration.
Figure 31 shows a simplified diagram for a single channel of the
AD5405. The feedback resistor RFBA has a value of 2R. The
value of R is typically 10 kΩ (with a minimum of 8 kΩ and a
maximum of 13 kΩ). If IOUT1A and IOUT2A are kept at the same
potential, a constant current flows into each ladder leg,
regardless of digital input code. Therefore, the input resistance
presented at VREFA is always constant.
VREFA
IOUT 2A
DAC DATA LATCHES
AND DRIVERS
2R
S1
2R
S2
2R
S3
2R
S12
2R
R
IOUT1A
RFB A
R
04463-005
Figure 31. Simplified Ladder Configuration
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of
the DAC, making the device extremely versatile and allowing it
to be configured for several operating modes, such as unipolar
output, bipolar output, or single-supply mode.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, this DAC can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 32.
RFB
2R
R1
2R
AD5405
12-Bit DAC A
R
R1A
RFBA
VDD
VREFA
VOUT = 0V TO –VIN
A1
IOUT2A
IOUT1A
AGND
C1
GND
AGND
R2A
R2_3A
R3A
R2
2R
R3
2R
AGND
04463-
006
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 32. Unipolar Operation
When an output amplifier is connected in unipolar mode, the
output voltage is given by
n
REF
OUT
D
V
2
×
=
where:
D
is the fractional representation, in the range of 0 to 4,095, of
the digital word loaded to the DAC.
n
is the resolution of the DAC.
With a fixed 10 V reference, the circuit shown in Figure 32 gives
a unipolar 0 V to 10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation.
Table 5. Unipolar Code
Digital Input
Analog Output (V)
1111 1111 1111
VREF (4,095/4,096)
1000 0000 0000
VREF (2,048/4,096) = VREF/2
0000 0000 0001
VREF (1/4,096)
0000 0000 0000
VREF (0/4,096) = 0
Bipolar Operation
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier, as shown in Figure 33.
RFB
2R
R1
2R
AD5405
12-Bit DAC A
R
R1A
RFBA
VDD
VREFA
R2A
R2_3A
R3A
A1
IOUT2A
IOUT1A
AGND
C1
R2
2R
R3
2R
AGND
GND
AGND
A1
VIN
VOUT =–VIN TO +VIN
04463-
007
NOTES
1. SIMILAR CONFIGURATION FOR DAC B.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 33. Bipolar Operation (4-Quadrant Multiplication)
When in bipolar mode, the output voltage is given by
REF
n
REF
OUT
V
D
V
×
=
)
2
(
1
where:
D
is the fractional representation, in the range of 0 to 4,095, of
the digital word loaded to the DAC.
n
is the number of bits.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
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