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參數(shù)資料
| 型號(hào)： | AD5410ACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SRL 40LFCSP |
| 設(shè)計(jì)資源： | Simplified 12-Bit, 4 mA-to-20 mA Output Solution Using AD5410 (CN0081) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 40µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 950mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電流，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD5410ACPZ-REEL7DKR |
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Data Sheet
AD5410/AD5420
Rev. F | Page 27 of 32
APPLICATIONS INFORMATION
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, connect a 0.01 F
capacitor between IOUT and GND. This ensures stability with
loads beyond 50 mH. There is no maximum capacitance limit.
The capacitive component of the load may cause slower settling.
Alternatively, the capacitor can be connected from CAP1 and/or
CAP2 to AVDD to reduce the slew rate of the current. The digital
slew rate control feature may also prove useful in this situation.
TRANSIENT VOLTAGE PROTECTION
The AD5410/AD5420 contain ESD protection diodes that prevent
damage from normal handling. The industrial control environ-
ment can, however, subject I/O circuits to much higher transients.
transients, external power diodes and a surge current limiting
resistor may be required, as shown in Figure 51. The constraint
on the resistor value is that during normal operation, the output
level at IOUT must remain within its voltage compliance limit of
AVDD 2.5 V, and the two protection diodes and resistor must
have appropriate power ratings. Further protection can be pro-
vided with transient voltage suppressors (TVS), or transorbs.
These are available as both unidirectional suppressors (protect
against positive high voltage transients) and bidirectional
suppressors (protect against both positive and negative high
voltage transients) and are available in a wide range of standoff
and breakdown voltage ratings. It is recommended that all field
connected nodes be protected.
AD5410/
AD5420
IOUT
RP
RL
07027-
039
AVDD
GND
Figure 51. Output Transient Voltage Protection
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board (PCB) on
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5410/AD5420 are in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
10 F in parallel with 0.1 F on each supply, located as close to
the package as possible, ideally right up against the device.
The 10 F capacitors are the tantalum bead type. The 0.1 F
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
large a trace as possible to provide low impedance paths and to
reduce the effects of glitches on the power supply line. Fast-
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board and
should never be run near the reference inputs. A ground line
routed between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board that has a
separate ground plane, but separating the lines helps). It is
essential to minimize noise on the REFIN line because noise
can couple through to the DAC output.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board.
A microstrip technique is by far the best method but is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground
plane, and signal traces are placed on the solder side.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler family of products from Analog Devices, Inc.,
provides voltage isolation in excess of 2.5 kV. The serial loading
because the number of interface lines is kept to a minimum.
AD5420 using an ADuM1400. For further information, visit
ENCODE
VIA
VOA
DECODE
ENCODE
VIB
VOB
DECODE
ENCODE
VIC
VOC
DECODE
ENCODE
TO
SCLK
TO
SDIN
TO
LATCH
TO
CLEAR
SERIAL
CLOCK
OUT
CONTROLLER
ADuM1400*
*ADDITIONAL PINS OMITTED FOR CLARITY.
SERIAL
DATA
OUT
SYNC
OUT
CONTROL
OUT
VID
VOD
DECODE
07027-
040
Figure 52. Isolated Interface
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