參數(shù)資料
型號(hào)： AD5412ACPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/44頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT SER 40-LFCSP
設(shè)計(jì)資源： Simplified 12-Bit Voltage and 4 mA-to-20 mA Output Solution Using AD5412 (CN0097)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 25µs
位數(shù)： 12
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 128mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類(lèi)型： 1 電流，單極；1 電流，雙極；1 電壓，單極；1 電壓，雙極
采樣率（每秒）： 40k
產(chǎn)品目錄頁(yè)面： 782 (CN2011-ZH PDF)
其它名稱(chēng)： AD5412ACPZ-REEL7DKR
AD5412/AD5422
Data Sheet
Rev. I | Page 28 of 44
SERIAL INTERFACE
The AD5412/AD5422 are controlled over a versatile 3-wire
serial interface that operates at clock rates of up to 30 MHz. It is
compatible with SPI, QSPI, MICROWIRE, and DSP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the rising edge of
SCLK. The input register consists of eight address bits and
16 data bits, as shown in Table 7. The 24-bit word is uncondi-
tionally latched on the rising edge of the LATCH pin. Data
continues to be clocked in irrespective of the state of LATCH.
On the rising edge of LATCH, the data that is present in the
input register is latched; in other words, the last 24 bits to be
clocked in before the rising edge of LATCH is the data that is
latched. The timing diagram for this operation is shown in
Table 7. Input Shift Register Format
MSB
LSB
D23 to D16
D15 to D0
Address byte
Data-word
Table 8. Address Byte Functions
Address Word
Function
00000000
No operation (NOP)
00000001
Data register
00000010
Readback register value as per read address
01010101
Control register
01010110
Reset register
Standalone Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous SCLK source can be used
only if LATCH is taken high after the correct number of data
bits have been clocked in. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used, and
LATCH must be taken high after the final clock to latch the
data. The rising edge of SCLK that clocks in the MSB of the
data-word marks the beginning of the write cycle. Exactly 24
rising clock edges must be applied to SCLK before LATCH is
brought high. If LATCH is brought high before the 24th rising
SCLK edge, the data written is invalid. If more than 24 rising
SCLK edges are applied before LATCH is brought high, the
input data is also invalid.
CONTROLLER
DATA IN
DATA OUT
SERIAL CLOCK
CONTROL OUT
AD5412/
AD54221
SDO
SDIN
SCLK
LATCH
AD5412/
AD54221
SDO
SDIN
SCLK
LATCH
AD5412/
AD54221
SDO
SDIN
SCLK
LATCH
1ADDITIONAL PINS OMITTED FOR CLARITY.
06
99
6-
06
0
Figure 68. Daisy Chaining the AD5412/AD5422
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain the devices together as shown in Figure 68.
in reducing the number of serial interface lines. Daisy-chain
mode is enabled by setting the DCEN bit of the control register
to 1. The first rising edge of SCLK that clocks in the MSB of the
data-word marks the beginning of the write cycle. SCLK is
continuously applied to the input shift register. If more than 24
clock pulses are applied, the data ripples out of the shift register
and appears on the SDO line. This data is valid on the rising
edge of SCLK, having been clocked out on the previous falling
SCLK edge. By connecting the SDO of the first device to the
SDIN input of the next device in the chain, a multidevice
interface is constructed. Each device in the system requires
24 clock pulses. Therefore, the total number of clock cycles
must equal 24 × n, where n is the total number of AD5412/
AD5422 devices in the chain. When the serial transfer to all
devices is complete, LATCH is taken high. This latches the
input data in each device in the daisy chain. The serial clock
can be a continuous or a gated clock.
A continuous SCLK source can be used only if LATCH is taken
high after the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used, and LATCH must be taken high after the final
clock to latch the data (see Figure 4 for a timing diagram).
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