參數(shù)資料
型號(hào): AD5412AREZ
廠商: Analog Devices Inc
文件頁數(shù): 15/44頁
文件大?。?/td> 0K
描述: IC DAC 12BIT SER 24TSSOP
設(shè)計(jì)資源: Simplified 12-Bit Voltage and 4 mA-to-20 mA Output Solution Using AD5412 (CN0097)
標(biāo)準(zhǔn)包裝: 62
設(shè)置時(shí)間: 25µs
位數(shù): 12
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 128mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TSSOP 裸露焊盤
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極;1 電壓,單極;1 電壓,雙極
采樣率(每秒): 40k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
AD5412/AD5422
Data Sheet
Rev. I | Page 22 of 44
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
–40
–20
0
20
40
60
80
T
O
T
AL
UNAD
J
U
S
T
E
D
E
RR
O
R
(
%
F
S
R
)
TEMPERATURE (°C)
AVDD = 24V
AVSS = –24V/0V
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
06
996
-01
3
Figure 50. Total Unadjusted Error vs. Temperature
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
–40
–20
0
20406080
O
F
S
E
T
E
RRO
R
(
%
F
S
R)
TEMPERATURE (°C)
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
AVDD = 24V
AVSS = –24V/0V
06
99
6-
0
17
Figure 51. Offset Error vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
–40
–20
0
20
40
60
80
G
AI
N
E
RRO
R
(
%
F
S
R)
TEMPERATURE (°C)
AVDD = 24V
AVSS = –24V/0V
4mA TO 20mA INTERNAL RSET
0mA TO 20mA INTERNAL RSET
0mA TO 24mA INTERNAL RSET
4mA TO 20mA EXTERNAL RSET
0mA TO 20mA EXTERNAL RSET
0mA TO 24mA EXTERNAL RSET
06
99
6-
0
18
Figure 52. Gain Error vs. Temperature
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
10
15
20
25
30
35
40
INL
E
RRO
R
(
%
F
S
R)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
0
69
96
-01
1
Figure 53. Integral Nonlinearity Error vs. AVDD, External RSET
–0.015
–0.020
–0.010
–0.005
0.005
0.015
0
0.010
0.020
10
15
20
25
30
35
40
INL
E
RRO
R
(
%
F
S
R)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
06
99
6-
0
14
Figure 54. Integral Nonlinearity Error vs. AVDD, Internal RSET
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
10
15
20
25
30
35
40
DN
L
E
RRO
R
(L
S
B
)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
AVSS = 0V
0
69
96
-01
2
Figure 55. Differential Nonlinearity Error vs. AVDD, External RSET
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