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參數(shù)資料
| 型號(hào)： | AD5415YRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL MULT 24-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 120ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 3.5µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 2.47M |
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Data Sheet
AD5415
Rev. E | Page 21 of 28
Table 11. DAC Control Bits
C3
C2
C1
C0
DAC
Function
0
A and B
No operation (power-on default)
0
1
A
Load and update
0
1
0
A
Initiate readback
0
1
A
Load input register
0
1
0
B
Load and update
0
1
0
1
B
Initiate readback
0
1
0
B
Load input register
0
1
A and B
Update DAC outputs
1
0
A and B
Load input registers
1
0
1
–
Disable daisy-chain
1
0
1
0
–
Clock data to shift register on rising edge
1
0
1
–
Clear DAC output to zero scale
1
0
–
Clear DAC output to midscale
1
0
1
–
Control word
1
0
–
Reserved
1
–
No operation
SYNC Function
SYNC is an edge-triggered input that acts as a frame synchroni-
zation signal and chip enable. Data can only be transferred into
the device while SYNC is low. To start the serial data transfer,
SYNC should be taken low, observing the minimum SYNC
falling to SCLK falling edge setup time, t4.
Daisy-Chain Mode
Daisy-chain mode is the default mode at power on. To disable
the daisy-chain function, write 1001 to the control word. In
daisy-chain mode, the internal gating on SCLK is disabled.
SCLK is continuously applied to the input shift register when
SYNC is low. If more than 16 clock pulses are applied, the data
ripples out of the shift register and appears on the SDO line.
This data is clocked out on the rising edge of SCLK and is valid
for the next device on the falling edge of SCLK (default). By
connecting this line to the SDIN input on the next device in the
chain, a multidevice interface is constructed. For each device in
the system, 16 clock pulses are required. Therefore, the total
number of clock cycles must equal 16N, where N is the total
number of devices in the chain. (See Figure 5.)
When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents additional data from being clocked
into the input shift register. A burst clock containing the exact
number of clock cycles can be used, after which SYNC is taken
high. After the rising edge of SYNC, data is automatically trans-
ferred from each device’s input shift register to the addressed DAC.
When control bits are 0000, the device is in no-operation mode.
This might be useful in daisy-chain applications where the user
does not want to change the settings of a particular DAC in the
chain. Write 0000 to the control bits for that DAC, and subsequent
data bits are ignored.
Standalone Mode
After power on, writing 1001 to the control word disables daisy-
chain mode. The first falling edge of SYNC resets the serial clock
counter to ensure that the correct number of bits are shifted in and
out of the serial shift registers. A SYNC edge during the 16-bit
write cycle causes the device to abort the current write cycle.
After the falling edge of the 16th SCLK pulse, data is automati-
cally transferred from the input shift register to the DAC. For
another serial transfer to take place, the counter must be reset
by the falling edge of SYNC.
LDAC Function
The LDAC function allows asynchronous and synchronous
updates to the DAC output. The DAC is asynchronously updated
when this signal goes low. Alternatively, if this line is held per-
manently low, an automatic or synchronous update mode is
selected, whereby the DAC is updated on the 16th clock falling
edge when the device is in standalone mode, or on the rising
edge of SYNC when the device is in daisy-chain mode.
Software LDAC Function
Load-and-update mode also functions as a software update
function, irrespective of the voltage level on the LDAC pin.
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