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參數資料
| 型號： | AD5415YRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 16/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL MULT 24-TSSOP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 設置時間： | 120ns |
| 位數： | 12 |
| 數據接口： | 串行 |
| 轉換器數目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 3.5µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 2.47M |
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AD5415
Data Sheet
Rev. E | Page 22 of 28
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5415 DAC is through a
serial bus that uses standard protocol compatible with micro-
controllers and DSP processors. The communication channel is
a 3-wire interface consisting of a clock signal, a data signal, and
a synchronization signal. The AD5415 requires a 16-bit word,
with the default being data valid on the falling edge of SCLK;
however, this is changeable using the control bits in the data-word.
ADSP-21xx-to-AD5415 Interface
The ADSP-21xx family of DSPs is easily interfaced to the
AD5415 DAC without the need for extra glue logic. Figure 42
is an example of an SPI interface between the DAC and the
ADSP-2191. SCK of the DSP drives the serial data line, SDIN.
SYNC is driven from a port line, in this case SPIxSEL.
SCLK
SCK
SYNC
SPIxSEL
SDIN
MOSI
ADSP-21911
1ADDITIONAL PINS OMITTED FOR CLARITY.
AD54151
04461-041
Figure 42. ADSP-2191 SPI-to-AD5415 Interface
A serial interface between the DAC and DSP SPORT is shown
in Figure 43. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after SPORT is enabled. In a
write sequence, data is clocked out on each rising edge of the
DSP’s serial clock and clocked into the DAC input shift register
on the falling edge of its SCLK. The update of the DAC output
takes place on the rising edge of the SYNC signal.
SCLK
SYNC
TFS
SDIN
DT
ADSP-2101/
ADSP-2103/
ADSP-21911
1ADDITIONAL PINS OMITTED FOR CLARITY.
04461-042
AD54151
Figure 43. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-AD5415 Interface
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame sync delay and frame sync setup-and-hold, data delay
and data setup-and-hold, and SCLK width. The DAC interface
expects a t4
(SYNC falling edge to SCLK falling edge setup time)
of 13 ns minimum. See the ADSP-21xx User Manual for
information on clock and frame SYNC frequencies for the
SPORT register.
Table 12 shows the setup for the SPORT control register.
Table 12. SPORT Control Register Setup
Name
Setting
Description
TFSW
1
Alternate framing
INVTFS
1
Active low frame signal
DTYPE
00
Right-justify data
ISCLK
1
Internal serial clock
TFSR
1
Frame every word
ITFS
1
Internal framing signal
SLEN
1111
16-bit data-word
ADSP-BF5xx-to-AD5415 Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the BlackFin
processor and the AD5415 DAC is shown in Figure 44. In this
configuration, data is transferred through the MOSI (master
output, slave input) pin. SYNC is driven by the SPIxSEL pin,
which is a reconfigured programmable flag pin.
SCLK
SCK
SYNC
SPIxSEL
SDIN
MOSI
ADSP-BF5xx1
1ADDITIONAL PINS OMITTED FOR CLARITY.
AD54151
04461-052
Figure 44. ADSP-BF5xx-to-AD5415 Interface
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 45. When SPORT is enabled,
initiate transmission by writing a word to the Tx register. The
data is clocked out on each rising edge of the DSP’s serial clock
and clocked into the DAC’s input shift register on the falling edge
of its SCLK. The DAC output is updated by using the transmit
frame synchronization (TFS) line to provide a SYNC signal.
SCLK
SYNC
TFS
SDIN
DT
ADSP-BF5xx1
1ADDITIONAL PINS OMITTED FOR CLARITY.
04461-051
AD54151
Figure 45. ADSP-BF5xx SPORT-to-AD5415 Interface
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