參數(shù)資料
型號： AD5428YRUZ
廠商： Analog Devices Inc
文件頁數(shù)： 16/33頁
文件大?。?/td> 0K
描述： IC DAC 8BIT DUAL MULT 20TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 75
設(shè)置時間： 30ns
位數(shù)： 8
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 3.3µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 21.3M
產(chǎn)品目錄頁面： 782 (CN2011-ZH PDF)
AD5428/AD5440/AD5447
Data Sheet
Rev. C | Page 22 of 32
PARALLEL INTERFACE
Data is loaded into the AD5428/AD5440/AD5447 in 8-, 10-, or
12-bit parallel word format. Control lines CS and R/W allow
data to be written to or read from the DAC register. A write
event takes place when CS and R/W are brought low, data
available on the data lines fills the shift register, and the rising
edge of CS latches the data and transfers the latched data-word
to the DAC register. The DAC latches are not transparent;
therefore, a write sequence must consist of a falling and rising
edge on CS to ensure that data is loaded into the DAC register
and its analog equivalent is reflected on the DAC output.
A read event takes place when R/W is held high and CS is
brought low. Data is loaded from the DAC register, goes back
into the input register, and is output onto the data line, where it
can be read back to the controller for verification or diagnostic
purposes. The input and DAC registers of these devices are not
transparent; therefore, a falling and rising edge of CS is required
to load each data-word.
MICROPROCESSOR INTERFACING
ADSP-21xx-to-AD5428/AD5440/AD5447 Interface
Figure 44 shows the AD5428/AD5440/AD5447 interfaced to
the ADSP-21xx series of DSPs as a memory-mapped device. A
single wait state may be necessary to interface the AD5428/
AD5440/AD5447 to the ADSP-21xx, depending on the clock
speed of the DSP. The wait state can be programmed via the
data memory wait state control register of the ADSP-21xx (see
the ADSP-21xx family’s user manual for details).
04462-
055
R/W
DB0 TO DB11
AD5428/
AD5440/
AD54471
ADDRESS
DECODER
CS
DATA 0 TO
DATA 23
ADDRESS BUS
ADDR0 TO
ADRR13
ADSP-21xx1
DATA BUS
DMS
WR
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. ADSP21xx-to-AD5428/AD5440/AD5447 Interface
8xC51-to-AD5428/AD5440/AD5447 Interface
Figure 45 shows the interface between the AD5428/AD5440/
AD5447 and the 8xC51 family of DSPs. To facilitate external
data memory access, the address latch enable (ALE) mode is
enabled. The low byte of the address is latched with this output
pulse during access to the external memory. AD0 to AD7 are
the multiplexed low order addresses and data bus, and they
require strong internal pull-ups when emitting 1s. During
access to external memory, A8 to A15 are the high order
address bytes. Because these ports are open drain, they also
require strong internal pull-ups when emitting 1s.
04462-
057
R/W
DB0 TO DB11
AD5428/
AD5440/
AD54471
ADDRESS
DECODER
CS
AD0 TO AD7
ADDRESS BUS
A8 TO A15
80511
DATA BUS
WR
1ADDITIONAL PINS OMITTED FOR CLARITY.
8-BIT
LATCH
ALE
Figure 45. 8xC51-to-AD5428/AD5440/AD5447 Interface
ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
Figure 46 shows a typical interface between the AD5428/
AD5440/AD5447 and the ADSP-BF5xx family of DSPs. The
asynchronous memory write cycle of the processor drives the
digital inputs of the DAC. The AMSx line is actually four
memory select lines. Internal ADDR lines are decoded into
AMS3–0, and then these lines are inserted as chip selects. The
rest of the interface is a standard handshaking operation.
04462-
056
R/W
DB0 TO DB11
AD5428/
AD5440/
AD54471
ADDRESS
DECODER
CS
DATA 0 TO
DATA 23
ADDRESS BUS
ADDR1 TO
ADRR19
ADSP-BF5xx1
DATA BUS
AMSx
AWE
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
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