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參數(shù)資料
型號： AD5429YRU-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 11/29頁
文件大小： 0K
描述： IC DAC DUAL 8BIT MULT 16-TSSOP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 2,500
設置時間： 30ns
位數(shù)： 8
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 3.5µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 16-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 2.47M
AD5429/AD5439/AD5449
Data Sheet
Rev. E | Page 18 of 28
ADDING GAIN
In applications in which the output voltage must be greater than
VIN, gain can be added with an additional external amplifier, or
it can be achieved in a single stage. Consider the effect of temper-
ature coefficients of the thin film resistors of the DAC. Simply
placing a resistor in series with the RFB resistor causes mismatches
in the temperature coefficients, resulting in larger gain temper-
ature coefficient errors. Instead, the circuit in Figure 42 shows
the recommended method of increasing the gain of the circuit.
R1, R2, and R3 should have similar temperature coefficients,
but they need not match the temperature coefficients of the
DAC. This approach is recommended in circuits in which
gains of greater than 1 are required.
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves
to many applications. If this type of DAC is connected as the
feedback element of an op amp and RFBA is used as the input
resistor, as shown in Figure 43, the output voltage is inversely
proportional to the digital input fraction, D.
For D = 1 2n, the output voltage is
(
)n
IN
OUT
V
D
V
/
=
/
=
2
1
/
As D is reduced, the output voltage increases. For small values of
the Digital Fraction D, it is important to ensure that the amplifier
does not saturate and the required accuracy is met. For example,
an 8-bit DAC driven with binary code of 0x10 (0001 0000)—that
is, 16 decimal—in the circuit of Figure 43 should cause the output
voltage to be 16 × VIN. However, if the DAC has a linearity speci-
fication of ±0.5 LSB, D can have a weight in the range of 15.5/256
to 16.5/256, so that the possible output voltage is in the range of
15.5 VIN to 16.5 VIN. This range represents an error of 3%, even
though the DAC itself has a maximum error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current into the VREFx terminal
is routed to the IOUT1 terminal, the output voltage changes as
follows:
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREFx terminal.
For a DAC leakage current of 10 nA, R = 10 k, and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
VDD
RFBA
IOUT1A
IOUT2A
C1
GND
VDD
VREFA
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
8-/10-/12-BIT
DAC
VIN
R1
R3
R2
VOUT
R1 =
R2R3
R2 + R3
GAIN =
R2 + R3
R2
04464-011
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 42. Increasing Gain of Current Output DAC
VIN
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
VREFA
VDD
RFBA
IOUT1A
IOUT2A
GND
VOUT
04464-
012
8-/10-/12-BIT
DAC
Figure 43. Current-Steering DAC Used as a Divider or Programmable Gain Element
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