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參數(shù)資料
| 型號： | AD5429YRU-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/29頁 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 8BIT MULT 16-TSSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 2,500 |
| 設置時間： | 30ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 3.5µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 2.47M |
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AD5429/AD5439/AD5449
Data Sheet
Rev. E | Page 22 of 28
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD54xx family of DACs is
through a serial bus that uses standard protocol and is compatible
with microcontrollers and DSP processors. The communication
channel is a 3-wire interface consisting of a clock signal, a data
signal, and a synchronization signal. The AD5429/AD5439/
AD5449 require a 16-bit word, with the default being data valid
on the falling edge of SCLK; however, this is changeable using
the control bits in the data-word.
ADSP-21xx-to-AD5429/AD5439/AD5449 Interface
The ADSP-21xx family of DSPs is easily interfaced to an AD5429/
AD5439/AD5449 DAC without the need for extra glue logic.
Figure 48 is an example of a serial peripheral interface (SPI)
between the DAC and the ADSP-2191. The MOSI (master output,
slave input) pin of the DSP drives the serial data line, SDIN.
SYNC is driven from a port line, in this case SPIxSEL.
SCLK
SCK
SYNC
SPIxSEL
SDIN
MOSI
ADSP-2191*
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5429/AD5439/
AD5449*
04464-
027
Figure 48. ADSP-2191 SPI-to-AD5429/AD5439/AD5449 Interface
The ADSP-2101/ADSP-2103/ADSP-2191 processor incorporates
channel synchronous serial ports (SPORT). A serial interface
between the DAC and DSP SPORT is shown in Figure 49. In this
interface example, SPORT0 is used to transfer data to the DAC
shift register. Transmission is initiated by writing a word to the Tx
register after SPORT has been enabled. In a write sequence, data
is clocked out on each rising edge of the DSP serial clock and
clocked into the DAC input shift register on the falling edge of
its SCLK. Updating of the DAC output takes place on the rising
edge of the SYNC signal.
SCLK
SYNC
TFS
SDIN
DT
ADSP-2101/
ADSP-2103/
ADSP-2191
*
*ADDITIONAL PINS OMITTED FOR CLARITY.
04464-
028
AD5429/AD5439/
AD5449*
Figure 49. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-
AD5429/AD5439/AD5449 Interface
Communication between two devices at a given clock speed is
possible when the following specifications are compatible: frame
SYNC delay and frame SYNC setup-and-hold, data delay and
data setup-and-hold, and SCLK width. The DAC interface expects
a t4 (SYNC falling edge to SCLK falling edge setup time) of 13 ns
minimum.
See the ADSP-21xx user manual at www.analog.com for details
on clock and frame SYNC frequencies for the SPORT register.
Table 12 shows the setup for the SPORT control register.
Table 12. SPORT Control Register Setup
Name
Setting
Description
TFSW
1
Alternate framing
INVTFS
1
Active low frame signal
DTYPE
00
Right-justify data
ISCLK
1
Internal serial clock
TFSR
1
Frame every word
ITFS
1
Internal framing signal
SLEN
1111
16-bit data-word
ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface
The ADSP-BF5xx family of processors has an SPI-compatible port
that enables the processor to communicate with SPI-compatible
devices. A serial interface between the BlackFin processor and
the AD5429/AD5439/AD5449 DAC is shown in Figure 50. In
this configuration, data is transferred through the MOSI pin.
SYNC is driven by the SPIxSEL pin, which is a reconfigured
programmable flag pin.
SCLK
SCK
SYNC
SPIxSEL
SDIN
MOSI
ADSP-BF5xx*
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5429/AD5439/
AD5449*
04464-
033
Figure 50. ADSP-BF5xx-to-AD5429/AD5439/AD5449 Interface
A serial interface between the DAC and the DSP SPORT is shown
in Figure 51. When SPORT is enabled, initiate transmission by
writing a word to the Tx register. The data is clocked out on each
rising edge of the DSP serial clock and clocked into the DAC
input shift register on the falling edge of its SCLK. The DAC
output is updated by using the transmit frame synchronization
(TFS) line to provide a SYNC signal.
SCLK
SYNC
TFS
SDIN
DT
ADSP-BF5xx*
*ADDITIONAL PINS OMITTED FOR CLARITY.
04464-
034
AD5429/AD5439/
AD5449*
Figure 51. ADSP-BF5xx SPORT-to-AD5429/AD5439/AD5449 Interface
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| AD5429YRU-REEL7 | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 8-bit 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:DAC 2CH R-2R 8BIT 16TSSOP - Tape and Reel |
| AD5429YRUZ | 功能描述:IC DAC DUAL 8BIT MULT 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5429YRUZ-REEL | 功能描述:IC DAC DUAL 8BIT MULT 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 設計資源:Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139) 標準包裝:10,000 系列:- 設置時間:- 位數(shù):12 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 薄型，TSOT-23-8 供應商設備封裝:TSOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:2.7M |
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