All input signals are specified with t
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD5429YRUZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 26/29闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DAC DUAL 8BIT MULT 16TSSOP
鐢㈠搧鍩硅〒妯″锛� Data Converter Fundamentals
DAC Architectures
妯欐簴鍖呰锛� 96
瑷疆鏅傞枔锛� 30ns
浣嶆暩(sh霉)锛� 8
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶
杞夋彌鍣ㄦ暩(sh霉)鐩細 2
闆诲闆绘簮锛� 鍠浕婧�
鍔熺巼鑰楁暎锛堟渶澶э級锛� 3.5µW
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 16-TSSOP锛�0.173"锛�4.40mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 16-TSSOP
鍖呰锛� 绠′欢
杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� 4 闆绘祦锛屽柈妤�锛�4 闆绘祦锛岄洐妤�
閲囨ǎ鐜囷紙姣忕锛夛細 2.47M
Data Sheet
AD5429/AD5439/AD5449
Rev. E | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
VREF = 10 V, IOUT2 = 0 V, temperature range for Y version: 40掳C to +125掳C. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
Limit at TMIN, TMAX
Unit
Conditions/Comments2
fSCLK
50
MHz max
Maximum clock frequency
t1
20
ns min
SCLK cycle time
t2
8
ns min
SCLK high time
t3
8
ns min
SCLK low time
t4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
4
ns min
Data hold time
t7
5
ns min
SYNC rising edge to SCLK falling edge
t8
30
ns min
Minimum SYNC high time
t9
0
ns min
SCLK falling edge to LDAC falling edge
t10
12
ns min
LDAC pulse width
t11
10
ns min
SCLK falling edge to LDAC rising edge
25
ns min
SCLK active edge to SDO valid, strong SDO driver
60
ns min
SCLK active edge to SDO valid, weak SDO driver
t13
12
ns min
CLR pulse width
t14
4.5
ns min
SYNC rising edge to LDAC falling edge
Update Rate
2.47
MSPS
Consists of cycle time, SYNC high time, data setup, and output voltage settling time
1
Guaranteed by design and characterization, not subject to production test.
2
Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
3
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5.
TIMING DIAGRAMS
t1
t2
t3
t7
t8
t4
t5
t6
t9
t10
t11
DB15
DB0
SCLK
SDIN
LDAC1
LDAC2
SYNC
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED.
04464-
002
Figure 2. Standalone Mode Timing Diagram
鐩搁棞PDF璩囨枡
PDF鎻忚堪
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MS27473T14F37SLC CONN HSG PLUG 37POS STRGHT SCKT
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AD5429YRUZ-REEL7 鍔熻兘鎻忚堪:IC DAC DUAL 8BIT MULT 16TSSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁鎻涘櫒 绯诲垪:- 鐢㈠搧鍩硅〒妯″:Data Converter Fundamentals DAC Architectures 瑷▓璩囨簮:Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139) 妯欐簴鍖呰:10,000 绯诲垪:- 瑷疆鏅傞枔:- 浣嶆暩(sh霉):12 鏁�(sh霉)鎿�(j霉)鎺ュ彛:DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? 杞夋彌鍣ㄦ暩(sh霉)鐩�:1 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:- 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:SOT-23-8 钖勫瀷锛孴SOT-23-8 渚涙噳鍟嗚ō鍌欏皝瑁�:TSOT-23-8 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:1 闆绘祦锛屽柈妤�锛�1 闆绘祦锛岄洐妤� 閲囨ǎ鐜囷紙姣忕锛�:2.7M
AD542JCHIPS 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:High Performance, BiFET Operational Amplifiers
AD542JH 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk
AD542JH/+ 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:- Bulk
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