參數(shù)資料
型號(hào): AD5429YRUZ
廠商: Analog Devices Inc
文件頁數(shù): 9/29頁
文件大?。?/td> 0K
描述: IC DAC DUAL 8BIT MULT 16TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 96
設(shè)置時(shí)間: 30ns
位數(shù): 8
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 3.5µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
輸出數(shù)目和類型: 4 電流,單極;4 電流,雙極
采樣率(每秒): 2.47M
AD5429/AD5439/AD5449
Data Sheet
Rev. E | Page 16 of 28
Bipolar Operation
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can easily be accomplished by using another external
amplifier and three external resistors, as shown in Figure 39.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. When connected in bipolar mode, the output
voltage is
(
)
REF
n
REF
OUT
V
D
V
/
×
=
/ 1
2
/
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)
n is the number of bits.
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation with the AD5429.
Table 6. Bipolar Code
Digital Input
Analog Output (V)
1111 1111
+VREF (255/256)
1000 0000
0
0000 0001
VREF (255/256)
0000 0000
VREF (256/256)
Stability
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as closely as possible, and
proper PCB layout techniques must be used. Because every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited gain bandwidth product (GBP) and
there is excessive parasitic capacitance at the inverting node.
This parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in the closed-
loop applications circuit.
As shown in Figure 38 and Figure 39, an optional compensation
capacitor, C1, can be added in parallel with RFBx for stability.
Too small a value of C1 can produce ringing at the output,
whereas too large a value can adversely affect the settling time.
C1 should be found empirically, but 1 pF to 2 pF is generally
adequate for the compensation.
04464-
008
IOUT1A
IOUT2A
AD5429/
AD5439/
AD5449
VREFx
VDD
C1
A1
VOUT = –VREF TO +VREF
R2
VDD
VREF ±10V
SDIN
SCLK
SYNC
MICROCONTROLLER
A2
R4
10k
R5
20k
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
4. DAC B AND ADDITIONAL PINS OMITTED FOR CLARITY.
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
R3 AND R4.
R3
20k
R1
RFBA
AGND
GND
R1
Figure 39. Bipolar Operation
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