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參數(shù)資料
| 型號： | AD5432YRM |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC MULTIPLYING 10BIT 10-MSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 設計資源： | Unipolar, Precision DC Digital-to-Analog Conversion Using AD5426/32/43 8-Bit to12-Bit DACs (CN0034) Precision, Bipolar Configuration for the AD5426/32/43 8-Bit to12-Bit DACs (CN0036) AC Signal Processing Using AD5426/32/43 Current Output DACs (CN0037) Programmable Gain Element Using AD5426/32/43 Current Output DACs (CN0038) |
| 標準包裝： | 50 |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2.5M |
AD5426/AD5432/AD5443
Data Sheet
Rev. G | Page 16 of 24
Bipolar Operation
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can easily be accomplished by using another external
amplifier and some external resistors, as shown in Figure 42.
In this circuit, the second amplifier, A2, provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data, D, which
is incremented from code zero (VOUT = VREF) to midscale
(VOUT = 0 V) to full scale (VOUT = +VREF).
REF
n
REF
OUT
V
D
V
×
=
1
2
where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.
D = 0 to 255 (8-bit AD5426)
= 0 to 1023 (10-bit AD5432)
= 0 to 4095 (12-bit AD5443)
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication.
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation (AD5426,
8-bit device).
Table 6. Bipolar Code Table
Digital Input
Analog Output (V)
1111 1111
+VREF (127/128)
1000 0000
0
0000 0001
VREF (127/128)
0000 0000
VREF (128/128)
Stability
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as close as possible and
proper PCB layout techniques must be employed. Since every
code change corresponds to a step function, gain peaking may
occur if the op amp has limited gain bandwidth product (GBP)
and there is excessive parasitic capacitance at the inverting node.
This parasitic capacitance introduces a pole into the open-loop
response that can cause ringing or instability in closed-loop
applications.
An optional compensation capacitor, C1, can be added in parallel
small a value of C1 can produce ringing at the output, while
too large a value can adversely affect the settling time. C1 should
be found empirically, but 1 pF to 2 pF is generally adequate for
compensation.
VOUT = –VREF
TO +VREF
SCLK SDIN GND
VREF
±10V
SYNC
IOUT2
IOUT1
RFB
AGND
AD5426/
AD5432/
AD5443
R1
R2
A1
VREF
VDD
C1
NOTES
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR
VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH
SPEED AMPLIFIER.
MICROCONTROLLER
R4
10k
R5
20k
R3
20k
A2
A1
03162-043
Figure 42. Bipolar Operation
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