參數(shù)資料
型號(hào): AD5440YRU
廠商: Analog Devices Inc
文件頁數(shù): 13/33頁
文件大?。?/td> 0K
描述: IC DAC 10BIT DUAL MULT 24-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 62
設(shè)置時(shí)間: 35ns
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 3.3µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 21.3M
Data Sheet
AD5428/AD5440/AD5447
Rev. C | Page 19 of 32
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 40 shows the DACs operating in voltage-switching
mode. The reference voltage, VIN, is applied to the IOUTA pin,
and the output voltage is available at the VREFA terminal. In this
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at constant impedance (the
DAC ladder resistance). Therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code.
Therefore, the voltage input should be driven from a low
impedance source.
Note that VIN is limited to low voltages because the switches in
the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and degrades the
integral linearity of the DAC. Also, VIN must not go negative by
more than 0.3 V, or an internal diode turns on, causing the
device to exceed the maximum ratings. In this type of
application, the full range of multiplying capability of the DAC
is lost.
04462-033
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
VDD
VIN
VREFA
VDD
RFBA
GND
VOUT
IOUTA
AGND
R1
R2
Figure 40. Single-Supply Voltage-Switching Mode
Positive Output Voltage
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistor’s tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and –2.5 V, respectively, as shown in Figure 41.
04462-034
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
VDD = 5V
VDD
C1
VIN
VREFA
RFBA
8-/10-/12-BIT
DAC
ADR03
GND
VOUT
VOUT =
0V to 2.5V
IOUTA
AGND
+5V
–5V
–2.5V
Figure 41. Positive Voltage Output with Minimum Components
ADDING GAIN
In applications where the output voltage must be greater than
VIN, gain can be added with an additional external amplifier, or
it can be achieved in a single stage. Consider the effect of temper-
ature coefficients of the thin film resistors of the DAC. Simply
placing a resistor in series with the RFB resistor causes mismatches
in the temperature coefficients, resulting in larger gain temper-
ature coefficient errors. Instead, the circuit in Figure 42 shows
the recommended method for increasing the gain of the circuit.
R1, R2, and R3 should have similar temperature coefficients,
but they need not match the temperature coefficients of the
DAC. This approach is recommended in circuits where gains of
greater than 1 are required.
04462-035
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
VDD
C1
VIN
VREFA
RFBA
R1
R3
R2
8-/10-/12-BIT
DAC
GND
VOUT
IOUTA
AGND
R2 + R3
R2
GAIN =
R1 =
R2R3
R2 + R3
Figure 42. Increasing Gain of Current Output DAC
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