參數(shù)資料
型號(hào)： AD5440YRU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/33頁(yè)
文件大小： 0K
描述： IC DAC 10BIT DUAL MULT 24-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 62
設(shè)置時(shí)間： 35ns
位數(shù)： 10
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 3.3µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 21.3M
AD5428/AD5440/AD5447
Data Sheet
Rev. C | Page 16 of 32
GENERAL DESCRIPTION
DAC SECTION
The AD5428/AD5440/AD5447 are CMOS 8-, 10-, and 12-bit,
dual-channel, current output DACs consisting of a standard
inverting R-2R ladder configuration. Figure 37 shows a simplified
diagram for a single channel of the 8-bit AD5428. The feedback
resistor RFBA has a value of R. The value of R is typically 10 kΩ
(with a minimum of 8 kΩ and a maximum of 12 kΩ). If IOUT1
and AGND are kept at the same potential, a constant current
flows into each ladder leg, regardless of digital input code.
Therefore, the input resistance presented at VREFA is always
constant and nominally of value R. The DAC output (IOUT) is
code-dependent, producing various resistances and
capacitances. When choosing an external amplifier, take into
account the variation in impedance generated by the DAC on
the amplifier’s inverting input node.
04462-029
VREF
DAC DATA LATCHES
AND DRIVERS
RFBA
IOUTA
AGND
RR
R
2R
S1
S2
S3
S8
Figure 37. Simplified Ladder
Access is provided to the VREF, RFB, and IOUT terminals of DAC A
and DAC B, making the devices extremely versatile and
allowing them to be configured in several operating modes,
such as unipolar output mode, 4-quadrant multiplication
bipolar mode, or single-supply mode. Note that a matching
switch is used in series with the internal RFBA feedback resistor.
If users attempt to measure RFBA, power must be applied to VDD
to achieve continuity.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 38. When an output amplifier
is connected in unipolar mode, the output voltage is given by
n
REF
OUT
D
V
2
/
×
=
where:
D
is the fractional representation of the digital word loaded to
the DAC.
D
= 0 to 255 (8-bit AD5428)
= 0 to 1023 (10-bit AD5440)
= 0 to 4095 (12-bit AD5447)
n
is the resolution of the DAC.
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages. These DACs are designed to
operate with either negative or positive reference voltages. The
VDD power pin is only used by the internal digital logic to drive
the on and off states of the DAC switches.
These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.
With a fixed 10 V reference, the circuit in Figure 38 gives a
unipolar 0 V to –10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 7 shows the relationship between digital code and the
expected output voltage for unipolar operation using the 8-bit
AD5428.
Table 7. Unipolar Code
Digital Input
Analog Output (V)
1111 1111
–VREF (255/256)
1000 0000
–VREF(128/256) = –VREF/2
0000 0001
–VREF (1/256)
0000 0000
–VREF (0/256) = 0
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