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| 型號： | AD5444YRM |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT MULTIPLYING 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 50 |
| 設(shè)置時間： | 16ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 50.5µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2.7M |
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AD5444/AD5446
Data Sheet
Rev. E | Page 18 of 28
04588-
035
NOTES:
1. ADDITIONAL PINS OMITTED FOR CLARITY.
IOUT1
GND
VOUT
VIN
RFB
VDD
VREF
VDD
Figure 43. Current-Steering DAC Used as a Divider
or Programmable Gain Element
As D is reduced, the output voltage increases. For small values
of the digital fraction (D), it is important to ensure that the
amplifier does not saturate and the required accuracy is met.
For example, an 8-bit DAC driven with the binary code 0x10
(0001 0000), that is, 16 decimal, in the circuit of Figure 43,
should cause the output voltage to be 16 × VIN. However, if the
DAC has a linearity specification of ±0.5 LSB, then D can, in
fact, have a weight in the range of 15.5/256 to 16.5/256, so the
possible output voltage is in the range 15.5 VIN to 16.5 VIN. This
is an error of 3%, even though the DAC itself has a maximum
error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction (D) of the current into the VREF terminal
is routed to the IOUT1 terminal, the output voltage has to change,
as follows:
Output Error Voltage due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R equal to 10 k, and a gain
(1/D) of 16, the error voltage is 1.6 mV.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is
an amplifier with low input bias currents and low input offset
voltage. The input offset voltage of an op amp is multiplied by
the variable gain (due to the code-dependent output resistance
of the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed upon the desired change
in output between the two codes and gives rise to a differential
linearity error, which, if large enough, can cause the DAC to be
nonmonotonic.
The input bias current of an op amp also generates an offset
at the voltage output as a result of the bias current flowing
in the feedback resistor, RFB. Most op amps have input bias
currents low enough to prevent any significant errors in
12-bit applications.
Common-mode rejection of the op amp is important in voltage
switching circuits because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-bit, 10-bit, and 12-bit
resolutions.
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage switching
DAC circuit is determined largely by the output op amp. To
obtain minimum settling time in this configuration, it is impor-
tant to minimize capacitance at the VREF node (voltage output
node in this application) of the DAC. This is done by using low
input, capacitance buffer amplifiers and careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which, in turn, requires an amplifier that can handle
rail-to-rail signals. A large range of single-supply amplifiers is
available from Analog Devices, Inc. (see Table 8 and Table 9 for
suitable suggestions).
REFERENCE SELECTION
When selecting a reference for use with the AD5444/AD5446
current output DAC, pay attention to the output voltage tem-
perature coefficient specification. This parameter affects not
only the full-scale error but can also affect the linearity (INL
and DNL) performance. The reference temperature coefficient
should be consistent with the system accuracy specifications.
For example, an 8-bit system required to hold its overall speci-
fication to within 1 LSB over the temperature range 0°C to 50°C
dictates that the maximum system drift with temperature
should be less than 78 ppm/°C.
A 12-bit system with the same temperature range to overall
specification within 2 LSBs requires a maximum drift of
10 ppm/°C. By choosing a precision reference with low output
temperature coefficient, this error source can be minimized.
Table 7 suggests some of the dc references available from
Analog Devices that are suitable for use with this range of
current output DACs.
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| AD5444YRM-REEL | 功能描述:IC DAC 12BIT MULTIPLYING 10-MSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標準包裝:91 系列:- 設(shè)置時間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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