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參數(shù)資料
| 型號(hào)： | AD5451 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface |
| 中文描述： | 8/10/12/14-Bit高帶寬倍增DAC的串行接口 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 125K |
| 代理商： | AD5451 |
AD5450/AD5451/AD5452/AD5453
–
11
–
REV. PrD
PRELIMINARY TECHNICAL DATA
G E NE R A L D E SC R IP T ION
D A C SE C T ION
T he AD5450, AD5451, AD5452 and AD5453 are 8, 10,
12 and 14 bit current output DACs consisting of a
segmented (4-Bits) inverting R-2R ladder configuration.
T he feedback resistor R
FB
has a value of R. T he value of R
is typically 9.3k
(minimum 8k
and maximum 12k
).
If I
OUT 1
is kept at the same potential as GND, a constant
current flows in each ladder leg, regardless of digital input
code. T herefore, the input resistance presented at V
REF
is
always constant and nominally of value R. T he DAC
output (I
OUT
) is code-dependent, producing various
resistances and capacitances. External amplifier choice
should take into account the variation in impedance
generated by the DAC on the amplifiers inverting input
node.
Access is provided to the V
REF
, R
FB
, and I
OUT 1
terminals
of the DAC, making the device extremely versatile and
allowing it to be configured in several different operating
modes, for example, to provide a unipolar output and in
four quadrant multiplication in bipolar mode. Note that a
matching switch is used in series with the internal R
FB
feedback resistor. If users attempt to measure R
FB
, power
must be applied to V
DD
to achieve continuity.
SE R IA L INT E R F A C E
T he AD5450/AD5451/AD5452/AD5453 have an easy to
use 3-wire interface which is compatible with SPI/QSPI/
MicroWire and DSP interface standards. Data is written
to the device in 16 bit words. T his 16-bit word consists of
2 control bits and either 8, 10 12, or 14 data bits as shown
in Figure 2. T he AD5453 uses all 14 bits of DAC data.
T he AD5452 uses twelve bits and ignores the two LSBs,
similarly the AD5451 uses ten bits and ignores the four
LSBs, while the AD5450 uses eight bits and ignores the
last six bits.
DAC C ontrol Bits C 1, C 0
Control bits C1 and C0 the user to load and update the
new DAC code and to change the active clock edge. By
default the shift register clocks data in on the falling edge,
this can be changed via the control bits. In this case, the
DAC core is inoperative until the next data frame. A
power cycle resets this back to default condition.
On chip power on reset circuitry ensures the device
powers on with zeroscale loaded to the DAC register and
I
OUT
line.
T ABLE III. DAC CONT ROL BIT S
C 1
C 0
Funtion Implemented
0
0
1
1
0
1
0
1
Load and Update(Power On Default)
Reserved
Reserved
Clock Data to shift register On Rising Edge
SY N C
F unction
SYNC
is an edge-triggered input that acts as a frame
synchronization signal and chip enable. Data can only be
transferred into the device while
SYNC
is low. T o start
the serial data transfer,
SYNC
should be taken low ob-
serving the minimum
SY NC
falling to SC L K falling
edge setup time, t
4
.
After the falling edge of the 16th SCLK pulse, bring
SYNC high to transfer data from the input shift register to
the DAC register.
Figure 2b. AD5451 10 bit Input Shift Register Contents
Figure 2c. AD5452 12 bit Input Shift Register Contents
DB0 (LSB)
DB15 (MSB)
DATA BITS
C1
C0
X
X
X
X
CONTROL BITS
DB7 DB6 DB5 DB4
DB3 DB2
DB0
DB1
X
X
Figure 2a. AD5450 8 bit Input Shift Register Contents
DB0 (LSB)
DB15 (MSB)
X
X
DATA BITS
CONTROL BITS
DB5 DB4
DB3 DB2
DB0
DB1
C1
C0
DB7 DB6
DB8
DB9
X
X
DB0 (LSB)
DB15 (MSB)
DATA BITS
CONTROL BITS
DB7 DB6 DB5 DB4
DB3 DB2
DB0
DB1
C1
C0
DB11 DB10
DB8
DB9
X
X
DB0 (LSB)
DB15 (MSB)
DATA BITS
CONTROL BITS
DB9 DB8 DB7 DB6
DB5 DB4
DB2
DB3
C1
C0
DB13 DB12
DB10
DB11
DB0
DB1
Figure 2c. AD5453 14 bit Input Shift Register Contents
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PDF描述 |
|---|---|
| AD5452 | 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface |
| AD5452YRM | 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface |
| AD5453 | 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface |
| AD5450YUJ | JACK, RJ45, R.ANG, PCB |
| AD5451YUJ | Multiconductor Cable; Number of Conductors:4; Conductor Size AWG:22; No. Strands x Strand Size:7 x 30; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes; Conductor Material:Copper; Features:Unshielded RoHS Compliant: Yes |
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| AD5451YUJZ | 制造商:Analog Devices 功能描述:IC,CMOS 10-bit DAC,AD5451YUJZ |
| AD5451YUJZ-REEL | 功能描述:IC DAC 10BIT MULT TSOT23-8 RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 設(shè)計(jì)資源:Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139) 標(biāo)準(zhǔn)包裝:10,000 系列:- 設(shè)置時(shí)間:- 位數(shù):12 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:SOT-23-8 薄型，TSOT-23-8 供應(yīng)商設(shè)備封裝:TSOT-23-8 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:2.7M |
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