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參數(shù)資料
| 型號(hào)： | AD5451 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface |
| 中文描述： | 8/10/12/14-Bit高帶寬倍增DAC的串行接口 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 125K |
| 代理商： | AD5451 |
–
14
–
REV. PrD
AD5450/AD5451/AD5452/AD5453
PRELIMINARY TECHNICAL DATA
V
OUT
V
DD
GND
IOUT2
IOUT1
RFB
V
DD
V
REF
C
1
NOTES:
1
ADDITIONAL PINS OMITTED FOR CLARITY
2
C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
R
3
R
2
R
2
V
IN
R1 = R2R3
R2 + R3
GAIN = R2 + R3
R2
Figure 7. Increasing Gain of Current Output DAC
USE D AS A D IVID E R OR PROGRAMMABL E GAIN
E L E M E NT
Current Steering DACs are very flexible and lend
themselves to many different applications. If this type of
DAC is connected as the feedback element of an op-amp
and R
FB
is used as the input resistor as shown in Figure 8,
then the output voltage is inversely proportional to the
digital input fraction D. For D = 1-2
n
the output voltage
is
V
OUT
= -V
IN
/D = -V
IN
/(1-2
-n
)
V
OUT
V
DD
GND
V
IN
IOUT1
RFB
V
DD
V
REF
NOTES:
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 8. Current Steering DAC used as a divider or
Programmable Gain Element
As D is reduced, the output voltage increases. For small
values of the digital fraction D, it is important to ensure
that the arnplifier does not saturate and also that the
required accuracy is met. For example, an eight bit DAC
driven with the binary code 10H (00010000), i.e., 16
decimal, in the circuit of Figure 8 should cause the output
voltage to be sixteen times V
IN
. However, if the DAC has
a linearity specification of +/- 0.5LSB then D
can in fact have the weight anywhere in the range 15.5/256
to 16.5/256 so that the possible output voltage will be in
the range 15.5V
IN
to 16.5V
IN
—an error of + 3% even
though the DAC itself has a maximum error of 0.2%.
DAC leakage current is also a potential error source in
divider circuits. T he leakage current must be
counterbalanced by an opposite current supplied from the
op amp through the DAC. Since only a fraction D of the
current into the V
REF
terminal is routed to the I
OUT 1
ter-
minal, the output voltage has to change as follows:
Output Error Voltage Due to Dac Leakage
= (Leakage x R)/D
where R is the DAC resistance at the V
REF
terminal. For a
DAC leakage current of 10nA, R = 10 kilohm and a gain
(i.e., 1/D) of 16 the error voltage is 1.6mV.
R E F E R E NC E SE L E C T ION
When selecting a reference for use with the AD5426 series
of current output DACs, pay attention to the references
output voltage temperature coefficient specification. T his
parameter not only affects the full scale error, but can also
affect the linearity (INL and DNL) performance. T he
reference temperature coefficient should be consistent with
the system accuracy specifications. For example, an 8-bit
system required to hold its overall specification to within
1LSB over the temperature range 0-50
o
C dictates that the
maximum
system drift
with temperature should be less than
78ppm/
o
C. A 14-Bit system with the same temperature
range to overall specification within 2LSBs requires a
maximum drift of 10ppm/
o
C. By choosing a precision
reference with low output temperature coefficient this
error source can be minimized. T able IV. suggests some
of the suitable dc references available from Analog
Devices that are suitable for use with this range of current
output DACs.
A MPL IF IE R SE L E C T ION
T he primary requirement for the current-steering mode is
an amplifier with low input bias currents and low input
offset voltage. T he input offset voltage of an op amp is
multiplied by the variable gain (due to the code dependent
output resistance of the DAC) of the circuit. A change in
this noise gain between two adjacent digital fractions
produces a step change in the output voltage due to the
amplifier’s input offset voltage. T his output voltage
change is superimposed upon the desired change in output
between the two codes and gives rise to a differential
linearity error, which if large enough could cause the
DAC to be non-monotonic.
T he input bias curent of an op amp also generates an
offset at the voltage output as a result of the bias current
flowing in the feedback resistor R
FB
. Most op amps have
input bias currents low enough to prevent any significant
errors in 12-Bit applications, however for 14-Bit
applications some consideration should be given to
selecting an appropriate amplifier.
Common mode rejection of the op amp is important in
voltage switching circuits, since it produces a code
dependent error at the voltage output of the circuit. Most
op amps have adequate common mode rejection for use at
8-, 10- and 12-Bit resolution.
Provided the DAC switches are driven from true wideband
low impedance sources (V
IN
and AGND) they settle
quickly. Consequently, the slew rate and settling time of a
voltage switching DAC circuit is determined largely by
the output op amp. T o obtain minimum settling time in
this configuration, it is important to minimize capacitance
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