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| 型號(hào)： | AD5453 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface |
| 中文描述： | 8/10/12/14-Bit高帶寬倍增DAC的串行接口 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | AD5453 |
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AD5450/AD5451/AD5452/AD5453
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13
–
REV. PrD
PRELIMINARY TECHNICAL DATA
T able II. Bipolar Code T able
Digital Input
Analog Output (V)
1111 1111
1000 0000
0000 0001
0000 0000
+V
REF
(127/128)
0
-V
REF
(127/128)
-V
REF
(128/128)
S tability
In the I-to-V configuration, the I
OUT
of the DAC and the
inverting node of the op amp must be connected as close
as possible, and proper PCB layout techniques must be
employed. Since every code change corresponds to a step
function, gain peaking may occur if the op amp has
limited GBP and there is excessive parasitic capacitance at
the inverting node. T his parasitic capacitance introduces a
pole into the open loop response which can cause ringing
or instability in the closed loop applications circuit.
An optional compensation capacitor, C1 can be added in
parallel with R
FB
for stability as shown in figures 3 and 4.
T oo small a value of C1 can produce ringing at the
output, while too large a value can adversely affect the
settling time. C1 should be found empirically but 1-2pF is
generally adequate for the compensation.
SINGL E SUPPL Y A PPL IC A T IONS
Voltage Switching Mode of Operation
Figure 5 shows these DACs operating in the voltage-
switching mode. T he reference voltage, V
IN
is applied to
the I
OUT 1
pin, I
OUT 2
is connected to AGND and the
output voltage is available at the V
REF
terminal. In this
configuration, a positive reference voltage results in a
positive output voltage making single supply operation
possible. T he output from the DAC is voltage at a
constant impedance (the DAC ladder resistance). T hus an
op-amp is necessary to buffer the output voltage. T he
reference input no longer sees a constant input impedance,
but one that varies with code. So, the voltage input should
be driven from a low impedance source.
V
OUT
V
DD
GND
V
IN
IOUT1
RFB
V
DD
V
REF
NOTES:
1
ADDITIONAL PINS OMITTED FOR CLARITY
2
C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
R
2
R
1
Figure 5. Single Supply Voltage Switching Mode Operation.
It is important to note that V
IN
is limited to low voltages
because the switches in the DAC ladder no longer have
the same source-drain drive voltage. As a result their on
resistance differs and this degrades the integral linearity of
the DAC. Also, V
IN
must not go negative by more than
0.3V or an internal diode will turn on, exceeding the max
ratings of the device. In this type of application, the full
range of multiplying capability of the DAC is lost.
POSIT IV E OUT PUT V OL T A GE
Note that the output voltage polarity is opposite to the
V
REF
polarity for dc reference voltages. In order to achieve
a positive voltage output, an applied negative reference to
the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the
resistors tolerance errors. T o generate a negative
reference, the reference can be level shifted by an op amp
such that the V
OUT
and GND pins of the reference
become the virtual ground and -2.5V respectively as
shown in Figure 6.
V
OUT = 0 to +2.5V
V
DD = 5V
GND
IOUT2
IOUT1
RFB
V
DD
V
REF
C
1
NOTES:
1
ADDITIONAL PINS OMITTED FOR CLARITY
2
C1 PHASE COMPENSATION (1pF-5pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
GND
VIN
VOUT
ADR03
+
5V
-
5V
1/2 AD8552
1/2 AD8552
-2.5V
Figure 6. Positive Voltage output with minimum of
components.
A D D ING GA IN
In applications where the output voltage is required to be
greater than V
IN
, gain can be added with an additional
external amplifier or it can also be achieved in a single
stage. It is important to take into consideration the effect
of temperature coefficients of the thin film resistors of the
DAC. Simply placing a resistor in series with the RFB
resistor will causing mis-matches in the T emperature
coefficients resulting in larger gain temperature coefficient
errors. Instead, the circuit of Figure 7 is a recommended
method of increasing the gain of the circuit. R1, R2 and
R3 should all have similar temperature coefficients, but
they need not match the temperature coefficients of the
DAC. T his approach is recommended in circuits where
gains of great than 1 are required.
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