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參數資料
| 型號： | AD5520JST-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Per Pin Parametric Measurement Unit/Source Measure Unit |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP64 |
| 封裝： | MS-026BCD, LQFP-64 |
| 文件頁數： | 4/20頁 |
| 文件大?。?/td> | 763K |
| 代理商： | AD5520JST-REEL |
REV. A
–4–
AD5520
TIMING CHARACTERISTICS
1, 2
(AV
CC
= +15 V
5%, AV
EE
= –15 V
5%, AGND = 0 V, REFGND = 0 V, DGND = 0 V. All
specifications 0 C to 70 C, unless otherwise noted.)
DV
DD
Parameter
5 V
10%
3.3 V
Unit
Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
0
30
40
0
550
320
450
150
100
240
150
100
320
0
200
70
40
560
320
500
800
440
240
500
440
320
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μ
s min
ns min
ns min
ns min
CS
Falling Edge to
STB
Falling Edge Setup Time
STB
Pulse Width
STB
Rising Edge to
CS
Rising Edge Setup Time
Data Setup Time
CS
Falling Edge to CPCK Rising Edge Setup Time
CPCK Pulse Width
CPCK to
STB
Falling Edge Setup Time
STB
Rising Edge to QMx, CLxDETECT Valid
STB
Rising Edge to CPOH, CPOL Valid
Comparator Setup Time, MODE2, MODE3 settling
Comparator Hold Time
Comparator Output Delay Time
Comparator Strobe Pulse Width
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
t
11
t
10
t
13
t
12
CPCK
CPOH, CPOL
MEASVOUT
OR MEASIOUT
Figure 2. Comparator Timing
CPCK
AMx, ACx, FSEL,
MSEL, CPSEL
CS
QM4, QM5,
CLHDETECT,
CLLDETECT
CPOL, CPOH
STB
t
3
t
2
t
1
t
4
t
5
t
6
t
7
t
8
t
9
Figure 1. Timing Diagram
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| AD5520JSTZ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Per Pin Parametric Measurement Unit/Source Measure Unit |
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