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參數(shù)資料
| 型號(hào)： | AD5532HS |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface |
| 中文描述： | 32通道14位的高速3線串行接口數(shù)模轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 244K |
| 代理商： | AD5532HS |
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REV. 0
AD5532
–11–
FUNCTIONAL DESCRIPTION
The AD5532 can be thought of as consisting of 32 DACs and
an ADC (for SHA mode) in a single package. In DAC mode a
14-bit digital word is loaded into one of the 32 DAC registers
via the serial interface. This is then converted (with gain and
offset) into an analog output voltage (V
OUT
0–V
OUT
31).
To update a DAC’s output voltage the required DAC is addressed
via the serial port. When the DAC address and code have been
loaded the selected DAC converts the code.
On power-on, all the DACs, including the offset channel, are
loaded with zeros. The internal DAC outputs are at 50 mV
typical (negative full-scale). If the OFFS_IN pin is driven by
the on-board offset channel, the outputs V
OUT
0 to V
OUT
31 are
also at 50 mV on power-on since OFFS_IN = 50 mV, V
OUT
=
(Gain
×
V
DAC
)
–(Gain –1)
×
V
OFFS_IN
= 50 mV.
Output Buffer Stage—Gain and Offset
The function of the output buffer stage is to translate the 0 V–3 V
output of the DAC to a wider range. This is done by gaining up
the DAC output by 3.52/7 and offsetting the voltage by the
voltage on OFFS_IN pin.
AD5532-1/AD5532-3/AD5532-5:
V
OUT
= 3.52
×
V
DAC
– 2.52
×
V
OFFS_IN
AD5532-2:
V
OUT
= 7
×
V
DAC
– 6
×
V
OFFS_IN
V
DAC
is the output of the DAC.
V
OFFS_IN
is the voltage at the OFFS_IN pin.
The following table shows how the output range on V
OUT
relates
to the offset voltage supplied by the user:
Table I. Sample Output Voltage Ranges
V
OFFS_IN
(V)
V
DAC
(V)
V
OUT
(AD5532-1/-3/-5)
V
OUT
(AD5532-2)
0.5
1
0 to 3
0 to 3
–1.26 to +9.3
–2.52 to +8.04
Headroom Limited
–6 to +15
V
OUT
is limited only by the headroom of the output amplifiers.
V
OUT
must be within maximum ratings.
Offset Voltage Channel
The offset voltage can be externally supplied by the user at
OFFS_IN or it can be supplied by an additional offset volt-
age channel on the device itself. The offset can be set up in
two ways. In SHA mode the required offset voltage is set up
on V
IN
and acquired by the offset channel. In DAC mode the
code corresponding to the offset value is loaded directly into
the offset DAC. This offset channel’s DAC output is directly
connected to OFFS_OUT. By connecting OFFS_OUT to OFFS_IN
this offset voltage can be used as the offset voltage for the 32
output amplifiers. It is important to choose the offset so that
V
OUT
is within maximum ratings.
Reset Function
The reset function on the AD5532 can be used to reset all nodes
on this device to their power-on-reset condition. This is imple-
mented by applying a low-going pulse of between 50 ns and 150 ns
to the
TRACK
/
RESET
pin on the device. If the applied pulse is
less than 50 ns it is assumed to be a glitch and no operation
takes place. If the applied pulse is wider than 150 ns this pin
adopts its track function on the selected channel, V
IN
is switched
to the output buffer and an acquisition on the channel will not
occur until a rising edge of
TRACK
.
SHA Mode
In SHA mode the input voltage V
IN
is sampled and converted
into a digital word. The noninverting input to the output buffer
(gain and offset stage) is tied to V
IN
during the acquisition period
to avoid spurious outputs while the DAC acquires the correct
code. This is completed in 16
μ
s max. At this time the updated
DAC output assumes control of the output voltage. The output
voltage of the DAC is connected to the noninverting input of
the output buffer. Since the channel output voltage is effectively
the output of a DAC there is no droop associated with it. As
long as power is maintained to the device the output voltage will
remain constant until this channel is addressed again.
Analog Input (SHA Mode)
The equivalent analog input circuit is shown in Figure 17. The
Capacitor C1 is typically 20 pF and can be attributed to pin
capacitance and 32 off-channels. When a channel is selected, an
extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged
to the previously acquired voltage on that particular channel
so it must charge/discharge to the new level. It is essential that the
external source can charge/discharge this additional capaci-
tance within 1
μ
s–2
μ
s of channel selection so that V
IN
can be
acquired accurately. For this reason a low impedance source
is recommended.
C1
20pF
V
IN
ADDRESSED CHANNEL
C2
7.5pF
Figure 17. Analog Input Circuit
Large source impedances will significantly affect the performance
of the ADC. This may necessitate the use of an input buffer
amplifier.
TRACK
Function (SHA Mode)
Normally in SHA mode of operation,
TRACK
is held high and
the channel begins to acquire when it is addressed. However, if
TRACK
is low when the channel is addressed, V
IN
is switched to
the output buffer and an acquisition on the channel will not
occur until a rising edge of
TRACK
. At this stage the
BUSY
pin
will go low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and
V
IN
is free to change again without affecting this output value.
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