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參數(shù)資料
| 型號： | AD5532HS |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface |
| 中文描述： | 32通道14位的高速3線串行接口數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 244K |
| 代理商： | AD5532HS |
REV. 0
AD5532
–14–
MICROPROCESSOR INTERFACING
AD5532 to ADSP-21xx Interface
The ADSP-21xx family of DSPs are easily interfaced to the
AD5532 without the need for extra logic.
A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5532 on the falling edge of its SCLK. In
readback 16 bits of data are clocked out of the AD5532 on each
rising edge of SCLK and clocked into the DSP on the rising
edge of SCLK. D
IN
is ignored. The valid 14 bits of data will be
centered in the 16-bit RX register when using this configuration.
The SPORT control register should be set up as follows:
TFSW
= RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK
= 1, Internal Serial Clock
TFSR
= RFSR = 1, Frame Every Word
IRFS
= 0, External Framing Signal
ITFS
= 1, Internal Framing Signal
SLEN
= 1001, 10-Bit Data Words (SHA Mode Write)
SLEN
= 0111, 3
×
8-Bit Data Words (DAC Mode Write)
SLEN
= 1111, 16-Bit Data Words (Readback Mode)
Figure 20 shows the connection diagram.
SCLK
AD5532*
D
OUT
SYNC
D
IN
DR
TFS
RFS
DT
SCLK
ADSP-2101/
ADSP-2103*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. AD5532 to ADSP-2101/ADSP-2103 Interface
AD5532 to MC68HC11
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 User Manual
. SCK of the 68HC11 drives the SCLK of
the AD5532, the MOSI output drives the serial data line (D
IN
)
of the AD5532 and the MISO input is driven from D
OUT
. The
SYNC
signal is derived from a port line (PC7). When data is
being transmitted to the AD5532, the
SYNC
line is taken low
(PC7). Data appearing on the MOSI output is valid on the fall-
ing edge of SCK. Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. In order to trans-
mit 10-data bits in SHA mode it is important to left-justify the
data in the SPDR register. PC7 must be pulled low to start a
transfer. It is taken high and pulled low again before any further
read/write cycles can take place. A connection diagram is shown in
Figure 21.
SCLK
AD5532*
D
OUT
SYNC
D
IN
MISO
PC7
SCK
MC68HC11*
*ADDITIONAL PINS OMITTED FOR CLARITY
MOSI
Figure 21. AD5532 to MC68HC11 Interface
AD5532 to PIC16C6x/7x
The PIC16C6x/7x Synchronous Serial Port (SSP) is config-
ured as an SPI Master with the Clock Polarity bit = 0. This is
done by writing to the Synchronous Serial Port Control Register
(SSPCON). See user
PIC16/17 Microcontroller User Manual
. In
this example I/O port RA1 is being used to pulse
SYNC
and
enable the serial port of the AD5532. This microcontroller
transfers only eight bits of data during each serial transfer opera-
tion; therefore, two or three consecutive read/write operations
are needed depending on the mode. Figure 22 shows the connec-
tion diagram.
SCLK
PIC16C6x/7x*
D
OUT
SYNC
D
IN
SCK/RC3
AD5532*
*ADDITIONAL PINS OMITTED FOR CLARITY
SDO/RC5
SDI/RC4
RA1
Figure 22. AD5532 to PIC16C6x/7x Interface
AD5532 to 8051
The AD5532 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode
0. In this mode serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 23 shows how the 8051 is
connected to the AD5532. Because the AD5532 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5532
requires its data with the MSB first. Since the 8051 outputs the
LSB first, the transmit routine must take this into account.
8051*
SCLK
D
OUT
SYNC
D
IN
TxD
AD5532*
*ADDITIONAL PINS OMITTED FOR CLARITY
RxD
P1.1
Figure 23. AD5532 to 8051 Interface
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