參數(shù)資料
型號: AD5547BRU
廠商: Analog Devices Inc
文件頁數(shù): 10/20頁
文件大小: 0K
描述: IC DAC 16BIT DUAL 38-TSSOP
產品培訓模塊: Data Converter Fundamentals
DAC Architectures
設計資源: Precision, Unipolar, Inverting Conversion Using AD5547/57 DAC (CN0026)
Precision, Unipolar, Noninverting Configuration for the AD5547/57 DAC (CN0027)
Precision, Bipolar, Configuration for AD5547/AD5557 DAC (CN0028)
標準包裝: 1
設置時間: 500ns
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 55µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 38-TFSOP(0.173",4.40mm 寬)
供應商設備封裝: 38-TSSOP
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 2M
AD5547/AD5557
Data Sheet
Rev. D | Page 18 of 20
REFERENCE SELECTION
When selecting a reference for use with the AD55xx series of
current output DACs, pay attention to the output voltage,
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 10 lists some of the references
available from Analog Devices, Inc., that are suitable for use
with this range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed upon the desired change in output
between the two codes and gives rise to a differential linearity error,
which, if large enough, can cause the DAC to be nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit.
Provided that the DAC switches are driven from true wideband
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-switching
DAC circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, minimize capacitance
at the VREF node (the voltage output node in this application) of
the DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 11 and Table 12.
Table 10. Suitable Analog Devices Precision References
Part No.
Output Voltage (V)
Initial Tolerance (%)
Maximum Temperature
Drift (ppm/°C)
I
SS (mA)
Output Noise (V p-p)
Package(s)
10
0.05
3
1
20
SOIC-8
10
0.05
9
1
20
TSOT-5, SC70-5
5.0
0.06
3
1
10
SOIC-8
5.0
0.06
9
1
10
TSOT-5, SC70-5
2.5
0.1
3
1
6
SOIC-8
2.5
0.1
9
1
6
TSOT-5, SC70-5
3.0
0.1
3
1
10
SOIC-8
3.0
0.1
9
1
10
TSOT-5, SC70-5
2.048
0.05
3
0.5
1.75
SOIC-8, MSOP-8
2.50
0.04
3
0.5
1.75
SOIC-8, MSOP-8
3.00
0.04
3
0.5
2
SOIC-8, MSOP-8
5.00
0.04
3
0.5
3.4
SOIC-8, MSOP-8
2.500
0.04
3
0.8
3.5
SOIC-8, MSOP-8
5.000
0.04
3
0.8
8
SOIC-8, MSOP-8
2.5
0.16
9
0.12
5
TSOT-5
5.0
0.10
9
0.12
8
TSOT-5
Table 11. Suitable Analog Devices Precision Op Amps
Part No.
Supply Voltage (V)
V
OS Maximum
(V)
I
B Maximum
(nA)
0.1 Hz to 10 Hz
Noise (V p-p)
Supply Current (A)
Package(s)
±2 to ±20
25
0.1
0.5
600
SOIC-8 , PDIP-8
±2.5 to ±15
60
2
0.4
500
MSOP-8, SOIC-8
±5 to ±18
75
2
0.1
2300
MSOP-8, SOIC-8
±5 to ±15
75
12
0.077
3000
MSOP-8, SOIC-8
±5 to ±15
125
90
0.1
2000
SOIC-8, SOT-23-5
1.8 to 5
50
0.001
2.3
40
TSOT-5
1.8 to 5
50
0.001
2.3
40
MSOP-8, SOIC-8
2.7 to 5
65
0.001
2.3
1000
WLCSP-5, SOT-23-5
2.7 to 5
65
0.001
2.4
2000
TSOT-5
2.7 to 5
65
0.001
2.4
2000
MSOP-8, SOIC-8
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