參數(shù)資料
型號: AD5551BRZ
廠商: Analog Devices Inc
文件頁數(shù): 7/16頁
文件大小: 0K
描述: IC DAC 14BIT SERIAL-IN 8-SOIC
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1
設置時間: 1µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 6.05mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 1M
產(chǎn)品目錄頁面: 783 (CN2011-ZH PDF)
AD5551/AD5552
Rev. A | Page 15 of 16
APPLICATIONS INFORMATION
OPTOCOUPLER INTERFACE
The digital inputs of the AD5551/AD5552 are Schmitt-
triggered, so they can accept slow transitions on the digital
input lines. This makes these parts ideal for industrial applica-
tions where it may be necessary that the DAC is isolated from
the controller via optocouplers. Figure 29 illustrates such an
interface.
10F
0.1F
VOUT
VDD
POWER
GND
5V
REGULATOR
AD5551/
AD5552
10k
VDD
CS
DIN
10k
VDD
DIN
10k
VDD
SCLK
01
94
3-
0
29
Figure 29. AD5551/AD5552 in an Optocoupler Interface
DECODING MULTIPLE AD5551/AD5552S
The CS pin of the AD5551/AD5552 can be used to select one of
a number of DACs. All devices receive the same serial clock and
serial data, but only one device receives the CS signal at any one
time. The DAC addressed is determined by the decoder. There
is some digital feedthrough from the digital input lines. Using a
burst clock minimizes the effects of digital feedthrough on the
analog signal channels.
shows a typical circuit.
AD5551/
AD5552
CS
DIN
SCLK
VOUT
AD5551/
AD5552
CS
DIN
SCLK
VOUT
AD5551/
AD5552
CS
DIN
SCLK
VOUT
AD5551/
AD5552
CS
DIN
SCLK
VOUT
VDD
DGND
EN
CODED
ADDRESS
SCLK
DIN
ENABLE
DECODER
01
94
3-
0
30
Figure 30. Addressing Multiple AD5551/AD5552s
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