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參數(shù)資料
| 型號： | AD5555CRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT DUAL SRL IN 16TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 500ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 55µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2M |
| 產(chǎn)品目錄頁面： | 783 (CN2011-ZH PDF) |
AD5545/AD5555
Data Sheet
Rev. G | Page 12 of 24
APPLICATIONS INFORMATION
STABILITY
AD5545/AD5555
AD8628
VREF
IOUT
VO
VDD
RFB
U1
U2
C1
GND
02918- 0- 020
Figure 21. Operational Compensation Capacitor for Gain Peaking
Prevention
In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited GBP, and if there
is excessive parasitic capacitance at the inverting node.
An optional compensation capacitor, C1, can be added for
stability as shown in Figure 21. C1 should be found empirically,
but 6 pF is generally more than adequate for the compensation.
POSITIVE VOLTAGE OUTPUT
To achieve the positive voltage output, an applied negative
reference to the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the
resistors’ tolerance errors. To generate a negative reference, the
reference can be level shifted by an op amp such that the VOUT
and GND pins of the reference become the virtual ground and
2.5 V, respectively (see Figure 22).
AD5545/AD5555
1/2
AD8628
1/2
AD8620
ADR03
VREF
IOUT
VOUT VIN
VDD
GND
02918- 0- 021
VO
0 < VO < +2.5
RFB
U2
U1
+5V
V+
–5V
V–
+5V
–2.5V
U3
C1
U4
Figure 22. Positive Voltage Output Configuration
BIPOLAR OUTPUT
The AD5545/AD5555 is inherently a 2-quadrant multiplying
DAC. It can easily be set up for unipolar output operation. The
full-scale output polarity is the inverse of the reference input
voltage.
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing. This
is easily accomplished by using an additional external amplifier,
U4, configured as a summing amplifier (see Figure 23). In this
circuit, the second amplifier, U4, provides a gain of 2, which
increases the output span magnitude to 5 V. Biasing the external
amplifier with a 2.5 V offset from the reference voltage results in a
full 4-quadrant multiplying circuit. The transfer equation of this
circuit shows that both negative and positive output voltages are
created because the input data (D) is incremented from code zero
(VOUT = 2.5 V) to midscale (VOUT = 0 V) to full scale (VOUT =
+2.5 V).
VOUT = (D/32,768 1) × VREF (AD5545)
(3)
VOUT = (D/8192 1) × VREF (AD5555)
(4)
For the AD5545, the external resistance tolerance becomes the
dominant error that users should be aware of.
AD5545/AD5555
1/2
AD8620
1/2
AD8620
ADR03
VREF
IOUT
VOUT VIN
VDD
GND
02918- 0- 022
VO
–2.5 < VO < +2.5
RFB
U2
U3
U1
+5V
V+
–5V
5V
V–
U4
C1
C2
R1
10k
±0.01% 10k±0.01%
5k
±0.01%
R2
R3
Figure 23. Four-Quadrant Multiplying Application Circuit
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