參數(shù)資料
型號(hào)： AD5669RBCPZ-2-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/32頁(yè)
文件大小： 0K
描述： IC DAC 16BIT I2C/SRL 16LFCSP-WQ
標(biāo)準(zhǔn)包裝： 1,500
系列： denseDAC
設(shè)置時(shí)間： 2.5µs
位數(shù)： 16
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 8
電壓電源： 單電源
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-WQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP-WQ（4x4）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： *
采樣率（每秒）： 166k
Data Sheet
AD5629R/AD5669R
Rev. D | Page 27 of 32
LDAC FUNCTION
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin.
Synchronous LDAC
The DAC registers are updated after new data is read in. LDAC
can be permanently low or pulsed as in Figure 2.
Asynchronous LDAC
The outputs are not updated at the same time that the input
registers are written to. When LDAC goes low, the DAC
registers are updated with the contents of the input register.
Alternatively, the outputs of all DACs can be updated simulta-
neously using the software LDAC function by writing to Input
Register n and updating all DAC registers. Command 0011 is
reserved for this software LDAC function.
An LDAC register gives the user extra flexibility and control
over the hardware LDAC pin. Setting the LDAC bit register
to 0 for a DAC channel means that this channel’s update is
controlled by the LDAC pin. If this bit is set to 1, this channel
updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the LDAC pin.
It effectively sees the LDAC pin as being tied low. See Table 16
for the LDAC register mode of operation.
This flexibility is useful in applications where the user wants
to simultaneously update select channels while the rest of the
channels are synchronously updating. Writing to the DAC
using command 0110 loads the 8-bit LDAC register (DB7 to
DB0). The default for each channel is 0, that is, the LDAC pin
works normally. Setting the bits to 1 means the DAC channel
is updated regardless of the state of the LDAC pin. See Table 17
for the contents of the input shift register during the load LDAC
register mode of operation.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5629R/AD5669R
should have separate analog and digital sections. If the AD5629R/
AD5669R are in a system where other devices require an
AGND-to-DGND connection, the connection should be made
at one point only. This ground point should be as close as
possible to the AD5629R/AD5669R.
The power supply to the AD5629R/AD5669R should be
bypassed with 10 F and 0.1 F capacitors. The capacitors
should be as physically close as possible to the device, with the
0.1 F capacitor ideally right up against the device. The 10 F
capacitors are the tantalum bead type. It is important that the
0.1 F capacitor have low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 F capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the ground
plane only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
Table 16.
EE
AA
Register
LDAC
Load DAC Register
A
LDACE
A
Bits (DB7 to DB0)
A
LDACE
A
Pin
A
LDACE
A
Operation
0
1/0
Determined by
A
LDACE
A
pin.
1
X—don’t care
DAC channels update, overriding the
A
LDACE
A
pin. DAC channels see
A
LDACE
A
as 0.
Table 17. 32-Bit Input Shift Register Contents for
AA
LDACEE
AA
Register Function
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
to DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
X
DAC H
DAC G
DAC F
DAC E
DAC D
DAC C
DAC B
DAC A
Command bits (C3 to C0)
Address bits (A3 to A0)—
don’t cares
Don’t
cares
Setting
A
LDACE
A
bit to 1 overrides
A
LDACE
A
pin
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