參數(shù)資料
型號： AD5678BRUZ-2REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 13/28頁
文件大?。?/td> 0K
描述： IC DAC 12/16BIT SPI/SRL 16TSSOP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 1,000
設(shè)置時間： 6µs
位數(shù)： 12，16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
電壓電源： 單電源
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 8 電壓，單極
采樣率（每秒）： 95k
AD5678
Rev. C | Page 20 of 28
THEORY OF OPERATION
D/A SECTION
The AD5678 DAC is fabricated on a CMOS process. The archi-
tecture consists of a string of DACs followed by an output buffer
amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/°C
reference with an internal gain of 2. Figure 45 shows a block
diagram of the DAC architecture.
052
99
-005
DAC REGISTER
REF (+)
VDD
VOUT
GND
REF (–)
RESISTOR
STRING
OUTPUT
AMPLIFIER
(GAIN = +2)
Figure 45. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
×
=
N
REFIN
OUT
D
V
2
the ideal output voltage when using an internal reference is
given by
×
=
N
REFOUT
OUT
D
V
2
where:
D
= decimal equivalent of the binary code that is loaded to the
DAC register.
0 to 4,095 for AD5678 DAC C, D, E, F (12 bits).
0 to 65,535 for AD5678 DAC A, B, G, H (16 bits).
N
= the DAC resolution.
RESISTOR STRING
The resistor string section is shown in Figure 46. It is simply a
string of resistors, each of value R. The code loaded into the
DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
05
29
9-
0
6
TO OUTPUT
AMPLIFIER
R
Figure 46. Resistor String
INTERNAL REFERENCE
The AD5678 has an on-chip reference with an internal gain of
2. The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full-
scale output of 2.5 V. The AD5678-2 has a 2.5 V 5 ppm/°C
reference, giving a full-scale output of 5 V. The on-board
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a write to a
control register. See Table 7.
The internal reference associated with each part is available at
the VREFOUT pin. A buffer is required if the reference output is
used to drive external loads. When using the internal reference,
it is recommended that a 100 nF capacitor be placed between
the reference output and GND for reference stability.
Individual channel power-down is not supported while using
the internal reference.
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