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參數(shù)資料
| 型號(hào)： | AD5678BRUZ-2REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/28頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 12/16BIT SPI/SRL 16TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 12，16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 8 電壓，單極 |
| 采樣率（每秒）： | 95k |
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AD5678
Rev. C | Page 21 of 28
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 2 kΩ in parallel with
1,000 pF to GND. The source and sink capabilities of the output
is 1.5 V/μs with a to scale settling time of 10 μs.
SERIAL INTERFACE
The AD5678 has a 3-wire serial interface (SYNC, SCLK, and
DIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards as well as most DSPs. See
for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5678 compatible with high speed
DSPs. On the 32nd falling clock edge, the last data bit is clocked
in and the programmed function is executed, that is, a change
in DAC register contents and/or a change in the mode of
operation. At this stage, the SYNC line can be kept low or be
brought high. In either case, it must be brought high for a
minimum of 15 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when VIN = 2 V
than it does when VIN = 0.8 V, SYNC should be idled low
between write sequences for even lower power operation of the
part. As is mentioned previously, however, SYNC must be
brought high again just before the next write sequence.
Table 7. Command Definitions
Command
C3
C2
C1
C0
Description
0
Write to Input Register n
0
1
Update DAC Register n
0
1
0
Write to Input Register n, update all
(software LDAC)
0
1
Write to and update DAC Channel n
0
1
0
Power down/power up DAC
0
1
0
1
Load clear code register
0
1
0
Load LDAC register
0
1
Reset (power-on reset)
1
0
Set up internal REF register
1
0
1
Reserved
–
Reserved
1
Reserved
Table 8. Address Commands
Address (n)
A3
A2
A1
A0
Selected DAC
Channel
0
DAC A (16 bits)
0
1
DAC B (16 bits)
0
1
0
DAC C (12 bits)
0
1
DAC D (12 bits)
0
1
0
DAC E (12 bits)
0
1
0
1
DAC F (12 bits)
0
1
0
DAC G (16 bits)
0
1
DAC H (16 bits)
1
All DACs
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