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參數(shù)資料
| 型號(hào)： | AD5726YRSZ-1500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/20頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT QUAD SERIAL 20-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | iCMOS® |
| 設(shè)置時(shí)間： | 9µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 30mW 單極；240mW 雙極 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 784 (CN2011-ZH PDF) |
| 其它名稱： | AD5726YRSZ-1500RL7DKR |
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AD5726
Data Sheet
Rev. C | Page 14 of 20
SERIAL INTERFACE
The AD5726 is controlled over a versatile 3-wire serial interface
that operates at clock rates up to 30 MHz and is compatible with
SPI, QSPI, MICROWIRE, and DSP standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device MSB first as a 16-bit word under the control of a serial
clock input, SCLK. The input register consists of two address
bits, two don’t care bits, and 12 data bits as shown in Table 10.
The timing diagram for this operation is shown in Figure 2.
When CS is low, the data presented to the input, SDIN, is shifted
MSB first into the internal shift register on the rising edge of
SCLK. Once all 16 bits of the serial data-word have been input,
the load control LDAC is strobed, and the word is latched onto
the internaldatabus. The two address bits are decoded and used to
route the 12-bit data-word to the appropriate DAC data register.
Operation of CS and SCLK
The CS and SCLK pins are internally fed to the same logical OR
gate and, therefore, require careful attention during a load cycle
to avoid clocking in false data bits. As shown in the timing diagram
in Figure 2, SCLK must be halted high, or CS must be brought
high, during the last high portion of SCLK following the rising
edge that clocked in the last data bit. Otherwise, an additional
rising edge is generated by CS rising while SCLK is low, causing
CS to act as the clock and allowing a false data bit into the input
shift register. The same must also be considered for the beginning
of the data load sequence.
Coding
The AD5726 uses binary coding. The output voltage can be
calculated from the following equation:
(
)
4096
D
V
REFN
REFP
REFN
OUT
×
+
=
where D is the digital code in decimal.
Load DAC (LDAC)
When asserted, the LDAC pin is an asynchronous, active low,
digital input that transfers the contents of the input register to
the internal data bus, updating the addressed DAC output. New
data must not be programmed to the AD5726 while the LDAC
pin is low.
CLR and CLRSEL
The CLR control allows the user to perform an asynchronous
clear function. Asserting CLR loads all four DAC registers,
forcing the DAC outputs toeither zeroscale (0x000) or midscale
(0x800), depending on the state of CLRSEL as shown in Table 8.
The CLR function is asynchronous and independent of CS.
When CLR returns high, the DAC outputs remain at the clear
value until LDAC is strobed, reloading the individual DAC
registers with either the data held in the input register prior to
the clear or with new data loaded through the serial interface.
Table 8. CLR/CLRSEL Truth Table
CLR
CLRSEL
DAC Registers
0
Zero scale (0x000)
0
1
Midscale (0x800)
1
0
No change
1
No change
Table 9. DAC Address Word Decode Table
A1
A0
DAC Addressed
0
DAC A
0
1
DAC B
1
0
DAC C
1
DAC D
Table 10. Input Register Format
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
A1
A0
X
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
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| AD5726YRSZ-1REEL | 功能描述:IC DAC 12BIT QUAD SERIAL 20-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:iCMOS® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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