參數(shù)資料
型號(hào): AD5732RBREZ
廠商: Analog Devices Inc
文件頁數(shù): 20/32頁
文件大?。?/td> 0K
描述: IC DAC DUAL 14BIT SERIAL 24TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源: Software Configurable 14-Bit Dual-Channel Unipolar/Bipolar Voltage Output Using AD5732R (CN0090)
標(biāo)準(zhǔn)包裝: 62
設(shè)置時(shí)間: 10µs
位數(shù): 14
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 190mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TSSOP 裸露焊盤
包裝: 管件
輸出數(shù)目和類型: 2 電壓,單極;2 電壓,雙極
采樣率(每秒): 1.07M
產(chǎn)品目錄頁面: 784 (CN2011-ZH PDF)
AD5722R/AD5732R/AD5752R
Rev. D | Page 27 of 32
DAC REGISTER
The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer
is to take place (see Table 18). The data bits are in positions DB15 to DB0 for the AD5752R (see Table 19), DB15 to DB2 for the AD5732R
(see Table 20), and DB15 to DB4 for the AD5722R (see Table 21).
Table 19. Programming the AD5752R DAC Register
MSB
LSB
R/W
Zero
REG2
REG1
REG0
A2
A1
A0
DB15 to DB0
0
DAC address
16-bit DAC data
Table 20. Programming the AD5732R DAC Register
MSB
LSB
R/W
Zero
REG2
REG1
REG0
A2
A1
A0
DB15 to DB2
DB1
DB0
0
DAC address
14-bit DAC data
X
Table 21. Programming the AD5722R DAC Register
MSB
LSB
R/W
Zero
REG2
REG1
REG0
A2
A1
A0
DB15 to DB4
DB3
DB2
DB1
DB0
0
DAC address
12-bit DAC data
X
OUTPUT RANGE SELECT REGISTER
The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel, and the
range bits (R2, R1, R0) select the required output range (see Table 22 and Table 23).
Table 22. Programming the Required Output Range
MSB
LSB
R/W
Zero
REG2
REG1
REG0
A2
A1
A0
DB15 to DB3
DB2
DB1
DB0
0
1
DAC address
Don’t care
R2
R1
R0
Table 23. Output Range Options
R2
R1
R0
Output Range (V)
0
+5
0
1
+10
0
1
0
+10.8
0
1
±5
1
0
±10
1
0
1
±10.8
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