參數(shù)資料
型號(hào)： AD5732RBREZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/32頁(yè)
文件大?。?/td> 0K
描述： IC DAC DUAL 14BIT SERIAL 24TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： Software Configurable 14-Bit Dual-Channel Unipolar/Bipolar Voltage Output Using AD5732R (CN0090)
標(biāo)準(zhǔn)包裝： 62
設(shè)置時(shí)間： 10µs
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 190mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm）裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 24-TSSOP 裸露焊盤(pán)
包裝： 管件
輸出數(shù)目和類(lèi)型： 2 電壓，單極；2 電壓，雙極
采樣率（每秒）： 1.07M
產(chǎn)品目錄頁(yè)面： 784 (CN2011-ZH PDF)
AD5722R/AD5732R/AD5752R
Rev. D | Page 28 of 32
CONTROL REGISTER
The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the
control function selected. The control register options are shown in Table 24 and Table 25.
Table 24. Programming the Control Register
MSB
LSB
R/W
Zero
REG2
REG1
REG0
A2
A1
A0
DB15 to DB4
DB3
DB2
DB1
DB0
0
1
0
NOP, data = don’t care
0
1
0
1
Don’t care
TSD enable
Clamp enable
CLR select
SDO disable
0
1
0
Clear, data = don’t care
0
1
0
1
Load, data = don’t care
Table 25. Explanation of Control Register Options
Option
Description
NOP
No operation instruction used in readback operations.
Clear
Addressing this function sets the DAC registers to the clear code and updates the outputs.
Load
Addressing this function updates the DAC registers and, consequently, the DAC outputs.
SDO Disable
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
CLR Select
See Table 26 for a description of the CLR select operation.
Clamp Enable
Set by the user to enable the current limit clamp. The channel does not power down upon detection of an
overcurrent; the current is clamped at 20 mA (default).
Cleared by the user to disable the current-limit clamp. The channel powers down upon detection of an overcurrent.
TSD Enable
Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown
feature (default).
Table 26. CLR Select Options
Output CLR Value
CLR Select Setting
Unipolar Output Range
Bipolar Output Range
0
0 V
1
Midscale
Negative full scale
POWER CONTROL REGISTER
The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power
and thermal status of the AD5722R/AD5732R/AD5752R. The power control register options are shown in Table 27 and Table 28.
Table 27. Programming the Power Control Register
MSB
LSB
R/W
Zero
REG2
REG1
REG0
A2
A1
A0
DB15
to
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
X
OCB
X
OCA
0
TSD
PUREF
X
PUB
X
PUA
Table 28. Power Control Register Functions
Option
Description
PUA
DAC A power-up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down
mode (default). After setting this bit to power DAC A, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register
is cleared, DAC A powers down automatically on detection of an overcurrent, and PUA is cleared to reflect this.
PUB
DAC B power-up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down
mode (default). After setting this bit to power DAC B, a power-up time of 10 μs is required. During this power-up time the DAC
register should not be loaded to the DAC output (see the Load DAC (LDAC) section). If the clamp enable bit of the control register
is cleared, DAC B powers down automatically on detection of an overcurrent, and PUB is cleared to reflect this.
PUREF
Reference power-up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the
internal reference in power-down mode (default).
TSD
Thermal shutdown alert. Read-only bit. In the event of an overtemperature situation, both DACs are powered down and this bit is set.
OCA
DAC A overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC A, this bit is set.
OCB
DAC B overcurrent alert. Read-only bit. In the event of an overcurrent situation on DAC B, this bit is set.
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