Data Sheet
AD5735
Rev. C | Page 11 of 48
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter
Rating
AV
DD, VBOOST_x to AGND, DGND
0.3 V to +33 V
AV
SS to AGND, DGND
+0.3 V to 28 V
AV
DD to AVSS
0.3 V to +60 V
AV
CC to AGND
0.3 V to +7 V
DV
DD to DGND
0.3 V to +7 V
Digital Inputs to DGND
0.3 V to DV
DD + 0.3 V or +7 V
(whichever is less)
Digital Outputs to DGND
0.3 V to DV
DD + 0.3 V or +7 V
(whichever is less)
REFIN, REFOUT to AGND
0.3 V to AV
DD + 0.3 V or +7 V
(whichever is less)
V
OUT_x to AGND
AV
SS to VBOOST_x or 33 V if using
the dc-to-dc converter
+V
SENSE_x, VSENSE_x to AGND
AV
SS to VBOOST_x or 33 V if using
the dc-to-dc converter
I
OUT_x to AGND
AV
SS to VBOOST_x or 33 V if using
the dc-to-dc converter
SW
x to AGND
0.3 V to +33 V
AGND, GNDSW
x to DGND
0.3 V to +0.3 V
Operating Temperature Range (T
A)
40°C to +105°C
Storage Temperature Range
65°C to +150°C
Junction Temperature (T
J max)
125°C
Power Dissipation
(T
J max TA)/θJA
Lead Temperature
JEDEC industry standard
Soldering
J-STD-020
1 Power dissipated on chip must be derated to keep the junction temperature
below 125°C.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Junction-to-air thermal resistance (θJA) is specified for a JEDEC
4-layer test board.
Table 5. Thermal Resistance
Package Type
θ
JA
Unit
64-Lead LFCSP (CP-64-3)
28
°C/W
ESD CAUTION