Reducing AICC Current Requirements
參數(shù)資料
型號： AD5735ACPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 39/48頁
文件大?。?/td> 0K
描述： IC DAC QUAD VOLT CUR 64LFCSP
標(biāo)準(zhǔn)包裝： 750
設(shè)置時間： 18µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，4 電壓
采樣率（每秒）： *
AD5735
Data Sheet
Rev. C | Page 44 of 48
Reducing AICC Current Requirements
Two main methods can be used to reduce the AICC current
requirements. One method is to add an external compensation
resistor, and the other is to use slew rate control. These methods
can be used together.
Adding an External Compensation Resistor
A compensation resistor can be placed at the COMPDCDC_x pin
in series with the 10 nF compensation capacitor. A 51 k exter-
nal compensation resistor is recommended. This compensation
increases the slew time of the current output but reduces the AICC
transient current requirements. Figure 80 shows a plot of AICC
current for a 24 mA step through a 1 k load when using a 51 k
compensation resistor. The compensation resistor reduces the
current requirements through smaller loads even further, as
0
4
12
8
16
24
20
28
32
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(
A)
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
0.5
1.0
1.5
2.0
2.5
I O
UT
_
x
CURRE
NT
(
m
A
)/
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
09961-
185
Figure 80. AICC Current vs. Time for 24 mA Step Through 1 k Load
with External 51 k Compensation Resistor
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(
A)
0mA TO 24mA RANGE
500 LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
4
12
8
16
24
20
28
32
0
0.5
1.0
1.5
2.0
2.5
I O
UT
_
x
CURRE
NT
(
mA)
/V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
09961-
186
Figure 81. AICC Current vs. Time for 24 mA Step Through 500 Load
with External 51 k Compensation Resistor
Using Slew Rate Control
Using slew rate control can greatly reduce the current require-
ments of the AVCC supply, as shown in Figure 82.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
AI
CC
CURRE
NT
(
A)
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
0
4
12
8
16
24
20
28
32
0
1
2
3
4
5
6
I O
UT
_
x
CURRE
NT
(
m
A
)/
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
TIME (ms)
AICC
IOUT
VBOOST
09961-
187
Figure 82. AICC Current vs. Time for 24 mA Step Through 1 k Load
with Slew Rate Control
When using slew rate control, it is important to remember that
the output cannot slew faster than the dc-to-dc converter. The
dc-to-dc converter slews slowest at higher currents through large
loads (for example, 1 k). The slew rate is also dependent on
the configuration of the dc-to-dc converter. Two examples of
the dc-to-dc converter output slew are shown in Figure 80 and
Figure 81. (VBOOST corresponds to the output voltage of the
dc-to-dc converter.)
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