參數(shù)資料
型號: XC5VLX50T-1FFG665CES
廠商: Xilinx Inc
文件頁數(shù): 2/91頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 ES 50K 665FCBGA
產(chǎn)品變化通告: Step Intro and Pkg Change 11/March/2008
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LXT
LAB/CLB數(shù): 3600
邏輯元件/單元數(shù): 46080
RAM 位總計: 2211840
輸入/輸出數(shù): 360
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 665-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 665-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
10
Table 13: Processor Block MIB Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CPMMCCLK
1.146
1.247
1.463
ps
TCK_ADDRESS
CPMMCCLK
1.017
1.136
1.38
ps
TCK_DATA
CPMMCCLK
1.076
1.172
1.38
ps
TCONTROL_CK
CPMMCCLK
0.736
0.844
0.941
ps
TDATA_CK
CPMMCCLK
0.834
0.95
1.058
ps
Table 14: Processor Block PLBM Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CPMPPCMPLBCLK
0.971
1.095
1.354
ps
TCK_ADDRESS
CPMPPCMPLBCLK
1.215
1.372
1.673
ps
TCK_DATA
CPMPPCMPLBCLK
1.115
1.257
1.535
ps
TCONTROL_CK
CPMPPCMPLBCLK
1.7
1.79
1.86
ps
TDATA_CK
CPMPPCMPLBCLK
0.774
0.914
1.059
ps
Table 15: Processor Block PLBS0 Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CPMPPCS0PLBCLK
1.063
1.196
1.462
ps
TCK_DATA
CPMPPCS0PLBCLK
1.052
1.189
1.461
ps
TCONTROL_CK
CPMPPCS0PLBCLK
1.307
1.545
1.836
ps
TADDRESS_CK
CPMPPCS0PLBCLK
1.253
1.492
1.787
ps
TDATA_CK
CPMPPCS0PLBCLK
0.825
0.971
1.124
ps
Table 16: Processor Block PLBS1 Switching Characteristics
Clock Name
Description
Reference Clock
Speed Grade
Units
-3
-2
-1
Clock-to-out and setup relative to clock
TCK_CONTROL
CPMPPCS1PLBCLK
1.083
1.234
1.525
ps
TCK_DATA
CPMPPCS1PLBCLK
1.146
1.298
1.615
ps
TCONTROL_CK
CPMPPCS1PLBCLK
1.335
1.596
1.921
ps
TADDRESS_CK
CPMPPCS1PLBCLK
1.328
1.568
1.864
ps
TDATA_CK
CPMPPCS1PLBCLK
0.821
0.969
1.127
ps
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