參數(shù)資料
型號(hào)： XC5VLX50T-1FFG665CES
廠商： Xilinx Inc
文件頁(yè)數(shù)： 67/91頁(yè)
文件大?。?/td> 0K
描述： IC FPGA VIRTEX-5 ES 50K 665FCBGA
產(chǎn)品變化通告： Step Intro and Pkg Change 11/March/2008
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-5 LXT
LAB/CLB數(shù)： 3600
邏輯元件/單元數(shù)： 46080
RAM 位總計(jì)： 2211840
輸入/輸出數(shù)： 360
電源電壓： 0.95 V ~ 1.05 V
安裝類(lèi)型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 665-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 665-FCBGA
配用： 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
7
SelectIO DC Input and Output Levels
Values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended
operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and
VOH voltage levels shown. Other standards are sample tested.
Table 7: SelectIO DC Input and Output Levels
I/O Standard
VIL
VIH
VOL
VOH
IOL
IOH
V, Min
V, Max
V, Min
V, Max
V, Min
mA
LVTTL
–0.3
0.8
2.0
3.45
0.4
2.4
Note(3)
LVCMOS33,
LVDCI33
–0.3
0.8
2.0
3.45
0.4
VCCO – 0.4
Note(3)
LVCMOS25,
LVDCI25
–0.3
0.7
1.7
VCCO +0.3
0.4
VCCO – 0.4
Note(3)
LVCMOS18,
LVDCI18
–0.3
35% VCCO
65% VCCO
VCCO + 0.3
0.45
VCCO – 0.45
Note(4)
LVCMOS15,
LVDCI15
–0.3
35% VCCO
65% VCCO
VCCO + 0.3
25% VCCO
75% VCCO
Note(4)
LVCMOS12
–0.3
35% VCCO
65% VCCO
VCCO + 0.3
25% VCCO
75% VCCO
Note(6)
PCI33_3(5)
–0.2
30% VCCO
50% VCCO
VCCO
10% VCCO
90% VCCO
Note(5)
PCI66_3(5)
–0.2
30% VCCO
50% VCCO
VCCO
10% VCCO
90% VCCO
Note(5)
PCI-X(5)
–0.2
35% VCCO
50% VCCO
VCCO
10% VCCO
90% VCCO
Note(5)
GTLP
–0.3
VREF –0.1
VREF + 0.1
–
0.6
N/A
36
N/A
GTL
–0.3
VREF –0.05
VREF +0.05
–
0.4
N/A
32
N/A
HSTL I_12
–0.3
VREF –0.1
VREF +0.1
VCCO + 0.3
25% VCCO
75% VCCO
6.3
HSTL I(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO –0.4
8
–8
HSTL II(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO –0.4
16
–16
HSTL III(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO – 0.4
24
–8
HSTL IV(2)
–0.3
VREF –0.1
VREF +0.1
VCCO +0.3
0.4
VCCO – 0.4
48
–8
DIFF HSTL I(2)
–0.3
50% VCCO – 0.1 50% VCCO +0.1
VCCO +0.3
–
DIFF HSTL II(2)
–0.3
50% VCCO – 0.1 50% VCCO +0.1
VCCO +0.3
–
SSTL2 I
–0.3
VREF –0.15
VREF +0.15
VCCO +0.3
VTT –0.61
VTT + 0.61
8.1
–8.1
SSTL2 II
–0.3
VREF –0.15
VREF +0.15
VCCO +0.3
VTT –0.81
VTT + 0.81
16.2
–16.2
DIFF SSTL2 I
–0.3
50%
VCCO –0.15
50%
VCCO +0.15
VCCO +0.3
–
DIFF SSTL2 II
–0.3
50%
VCCO –0.15
50%
VCCO +0.15
VCCO +0.3
–
SSTL18 I
–0.3
VREF – 0.125
VREF + 0.125
VCCO +0.3
VTT –0.47
VTT + 0.47
6.7
–6.7
SSTL18 II
–0.3
VREF – 0.125
VREF +0.125
VCCO +0.3
VTT –0.60
VTT + 0.60
13.4
–13.4
DIFF SSTL18 I
–0.3
50%
VCCO –0.125
50%
VCCO +0.125
VCCO +0.3
–
DIFF SSTL18 II
–0.3
50%
VCCO –0.125
50%
VCCO +0.125
VCCO +0.3
–
Notes:
1.
Tested according to relevant specifications.
2.
Applies to both 1.5V and 1.8V HSTL.
3.
Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4.
Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5.
For more information on PCI33_3, PCI66_3, and PCI-X, refer to UG190: Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines.
6.
Supported drive strengths of 2, 4, 6, or 8 mA.
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XC5VLX50T-1FFG665I 功能描述:IC FPGA VIRTEX-5 50K 665FCBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-5 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VLX50T-2FF1136C 功能描述:IC FPGA VIRTEX-5 50K 1136FBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-5 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VLX50T-2FF1136CES 制造商:Xilinx 功能描述:
XC5VLX50T-2FF1136I 功能描述:IC FPGA VIRTEX-5 50K 1136FBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-5 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
XC5VLX50T-2FF665C 功能描述:IC FPGA VIRTEX-5 50K 665FCBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-5 LXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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