參數(shù)資料
型號(hào): XC5VLX50T-1FFG665CES
廠商: Xilinx Inc
文件頁(yè)數(shù): 19/91頁(yè)
文件大?。?/td> 0K
描述: IC FPGA VIRTEX-5 ES 50K 665FCBGA
產(chǎn)品變化通告: Step Intro and Pkg Change 11/March/2008
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LXT
LAB/CLB數(shù): 3600
邏輯元件/單元數(shù): 46080
RAM 位總計(jì): 2211840
輸入/輸出數(shù): 360
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 665-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 665-FCBGA
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
26
System Monitor Analog-to-Digital Converter Specification
Table 51: Analog-to-Digital Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
AVDD =2.5V±2%, VREFP = 2.5V, VREFN = 0V, ADCCLK = 5.2 MHz, TA =TMIN to TMAX, Typical values at TA=+25°C
DC Accuracy: All external input channels such as VP/VN and VAUXP[15:0]/VAUXN[15:0], Unipolar Mode,
and Common Mode = 0V
Resolution
10
Bits
Integral Nonlinearity
INL
±2
LSBs
Differential Nonlinearity
DNL
No missing codes (TMIN to TMAX)
Guaranteed Monotonic
±0.9
LSBs
Unipolar Offset Error(1)
Uncalibrated
±2
±30
LSBs
Bipolar Offset Error(1)
Uncalibrated measured in bipolar mode
±2
±30
LSBs
Gain Error(1)
Uncalibrated
±0.2
±2
%
Bipolar Gain Error(1)
Uncalibrated measured in bipolar mode
±0.2
±2
%
Total Unadjusted Error
(Uncalibrated)
TUE
Deviation from ideal transfer function.
VREFP –VREFN = 2.5V
±10
LSBs
Total Unadjusted Error
(Calibrated)
TUE
Deviation from ideal transfer function.
VREFP –VREFN = 2.5V
±1
±2
LSBs
Calibrated Gain Temperature
Coefficient
Variation of FS code with temperature
±0.01
LSB/°C
DC Common-Mode Reject
CMRRDC
VN = VCM = 0.5V ± 0.5V,
VP –VN = 100mV
70
dB
Conversion Rate(2)
Conversion Time - Continuous
tCONV
Number of CLK cycles
26
32
Conversion Time - Event
tCONV
Number of CLK cycles
21
T/H Acquisition Time
tACQ
Number of CLK cycles
4
DRP Clock Frequency
DCLK
DRP clock frequency
8
250
MHz
ADC Clock Frequency
ADCCLK
Derived from DCLK
1
5.2
MHz
CLK Duty cycle
40
60
%
Analog Inputs(3)
Dedicated Analog Inputs
Input Voltage Range
VP - VN
Unipolar Operation
0
1
Volts
Differential Inputs
–0.25
+0.25
Unipolar Common Mode Range (FS input)
0
+0.5
Differential Common Mode Range (FS input)
+0.3
+0.7
Bandwidth
20
MHz
Auxiliary Analog Inputs
Input Voltage Range
VAUXP[0] /VAUXN[0] to VAUXP[15]
/VAUXN[15]
Unipolar Operation
0
1
Volts
Differential Operation
–0.25
+0.25
Unipolar Common Mode Range (FS input)
0
+0.5
Differential Common Mode Range (FS input)
+0.3
+0.7
Bandwidth
10
kHz
Input Leakage Current
A/D not converting, ADCCLK stopped
±1.0
A
Input Capacitance
10
pF
On-chip Supply Monitor Error
VCCINT and VCCAUX with calibration enabled
±1.0
% Reading
On-chip Temperature Monitor
Error
–40°C to +125°C with calibration enabled
±4
°C
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