參數(shù)資料
型號(hào)： XC5VLX50T-1FFG665CES
廠商： Xilinx Inc
文件頁數(shù)： 32/91頁
文件大?。?/td> 0K
描述： IC FPGA VIRTEX-5 ES 50K 665FCBGA
產(chǎn)品變化通告： Step Intro and Pkg Change 11/March/2008
標(biāo)準(zhǔn)包裝： 1
系列： Virtex®-5 LXT
LAB/CLB數(shù)： 3600
邏輯元件/單元數(shù)： 46080
RAM 位總計(jì)： 2211840
輸入/輸出數(shù)： 360
電源電壓： 0.95 V ~ 1.05 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 665-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 665-FCBGA
配用： 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
38
Output Delay Measurements
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4” of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4” trace is
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure 11 and Figure 12.
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters VREF, RREF, CREF, and VMEAS fully describe
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
1.
Simulate the output driver of choice into the generalized
test setup, using values from Table 59.
2.
Record the time to VMEAS.
3.
Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
4.
Record the time to VMEAS.
5.
Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
X-Ref Target - Figure 11
Figure 11: Single Ended Test Setup
VREF
RREF
VMEAS
(voltage level when taking
delay measurement)
CREF
(probe capacitance)
FPGA Output
DS202_06_111608
X-Ref Target - Figure 12
Figure 12: Differential Test Setup
RREF VMEAS
+
–
CREF
FPGA Output
ds202_12_042808
Table 59: Output Delay Measurement Methodology
Description
I/O Standard
Attribute
RREF
(
Ω)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVTTL (all)
1M
0
1.4
0
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS33
1M
0
1.65
0
LVCMOS, 2.5V
LVCMOS25
1M
0
1.25
0
LVCMOS, 1.8V
LVCMOS18
1M
0
0.9
0
LVCMOS, 1.5V
LVCMOS15
1M
0
0.75
0
LVCMOS, 1.2V
LVCMOS12
1M
0
0.6
0
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI33_3 (rising edge)
25
10(2)
0.94
0
PCI33_3 (falling edge)
25
10(2)
2.03
3.3
PCI, 66 MHz, 3.3V
PCI66_3 (rising edge)
25
10(2)
0.94
0
PCI66_3 (falling edge)
25
10(2)
2.03
3.3
PCI-X, 133 MHz, 3.3V
PCIX (rising edge)
25
10(3)
0.94
PCIX (falling edge
25
10(3)
2.03
3.3
GTL (Gunning Transceiver Logic)
GTL
25
0
0.8
1.2
GTL Plus
GTLP
25
0
1.0
1.5
HSTL (High-Speed Transceiver Logic), Class I
HSTL_I
50
0
VREF
0.75
HSTL, Class II
HSTL_II
25
0
VREF
0.75
HSTL, Class III
HSTL_III
50
0
0.9
1.5
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