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| 型號： | AD5764RBSUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT QUAD VOUT 32-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5764(R), AD5744R Product Change 04/Sept/2009 |
| 設(shè)計(jì)資源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5764 (CN0006) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 275 mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電壓，雙極 |
| 產(chǎn)品目錄頁面： | 784 (CN2011-ZH PDF) |
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AD5764R
Data Sheet
Rev. D | Page 22 of 32
68HC11*
MISO
SYNC
SDIN
SCLK
MOSI
SCK
PC7
PC6
LDAC
SDO
SYNC
SCLK
LDAC
SDO
SYNC
SCLK
LDAC
SDO
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5764R*
06064-
061
Figure 40. Daisy-Chaining the AD5764R
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines. The first falling edge of SYNC
starts the write cycle. The SCLK is continuously applied to the
input shift register when SYNC is low. If more than 24 clock
pulses are applied, the data ripples out of the input shift register
and appears on the SDO line. This data is clocked out on the
rising edge of SCLK and is valid on the falling edge. By
connecting the SDO of the first device to the SDIN input of the
next device in the chain, a multidevice interface is constructed.
Each device in the system requires 24 clock pulses. Therefore,
the total number of clock cycles must equal 24n, where n is the
total number of AD5764R devices in the chain. When the serial
transfer to all devices is complete, SYNC is taken high. This
latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input shift
register. The serial clock can be a continuous or a gated clock.
A continuous SCLK source can be used only if SYNC is held
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
be used, and SYNC must be taken high after the final clock to
latch the data.
Readback Operation
Before a readback operation is initiated, the SDO pin must be
enabled by writing to the function register and clearing the SDO
disable bit; this bit is cleared by default. Readback mode is invoked
by setting the R/W bit to 1 in the serial input register write. With
R/W set to 1, Bit A2 to Bit A0, in association with Bit REG2 to
Bit REG0, select the register to be read. The remaining data bits in
the write sequence are don’t care. During the next SPI write, the
data appearing on the SDO output contains the data from the
previously addressed register. For a read of a single register, the
NOP command can be used in clocking out the data from the
selected register on SDO. The readback diagram in Figure 4
shows the readback sequence. For example, to read back the
fine gain register of Channel A, implement the following
sequence:
1. Write 0xA0XXXX to the input shift register. This write
configures the AD5764R for read mode with the fine gain
register of Channel A selected. Note that all the data bits,
DB15 to DB0, are don’t care.
2. Follow with a second write: an NOP condition, 0x00XXXX.
During this write, the data from the fine gain register is clocked
out on the SDO line; that is, data clocked out contains the
data from the fine gain register in Bit DB5 to Bit DB0.
SIMULTANEOUS UPDATING VIA LDAC
Depending on the status of both SYNC and LDAC, and after
data has been transferred into the input register of the DACs,
there are two ways to update the data registers and DAC outputs.
Individual DAC Updating
In individual DAC updating mode, LDAC is held low while data
is being clocked into the input shift register. The addressed DAC
output is updated on the rising edge of SYNC.
Simultaneous Updating of All DACs
In simultaneous updating of all DACs mode, LDAC is held high
while data is being clocked into the input shift register. All DAC
outputs are updated by taking LDAC low any time after SYNC
has been taken high. The update then occurs on the falling edge
of LDAC.
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