參數資料
| 型號： | AD5764RBSUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 3/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT QUAD VOUT 32-TQFP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產品變化通告： | AD5764(R), AD5744R Product Change 04/Sept/2009 |
| 設計資源： | High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5764 (CN0006) |
| 標準包裝： | 1 |
| 設置時間： | 8µs |
| 位數： | 16 |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 275 mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數目和類型： | 4 電壓，雙極 |
| 產品目錄頁面： | 784 (CN2011-ZH PDF) |
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Data Sheet
AD5764R
Rev. D | Page 11 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYNC
SCLK
SDIN
SDO
CLR
LDAC
D1
D0
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
RS
T
O
UT
R
S
TIN
DG
ND
DV
CC
AV
DD
P
G
ND
IS
CC
AV
SS
BI
N/
2sCO
M
P
AV
DD
AV
SS
T
EMP
RE
F
G
ND
RE
F
O
UT
RE
F
CD
RE
F
AB
1
2
3
4
5
6
7
8
23
22
21
18
19
20
24
17
PIN 1
9
10 11
12
13 14 15
16
32 31 30
29 28 27 26
25
AD5764R
TOP VIEW
(Not to Scale)
06064-
006
Figure 6. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
2
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This operates at clock
speeds of up to 30 MHz.
3
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
4
SDO
Serial Data Output. This pin is used to clock data from the serial register in daisy-chain or readback mode.
5
CLR
Negative Edge Triggered Input.1 Asserting this pin sets the data registers to 0x0000.
6
LDAC
Load DAC. This logic input is used to update the data registers and, consequently, the analog outputs. When
tied permanently low, the addressed data register is updated on the rising edge of SYNC. If LDAC is held high
during the write cycle, the DAC input register is updated but the output update is held off until the falling edge
of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC
pin must not be left unconnected.
7, 8
D0, D1
Digital I/O Port. D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are
configurable and readable over the serial interface. When configured as inputs, these pins have weak internal
pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND.
9
RSTOUT
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it
can be used to control other system components.
10
RSTIN
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input
clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain
unchanged.
11
DGND
Digital Ground Pin.
12
DVCC
Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.
13, 31
AVDD
Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.
14
PGND
Ground Reference Point for Analog Circuitry.
15, 30
AVSS
Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.
16
ISCC
This pin is used in association with an optional external resistor to AGND to program the short-circuit current
of the output amplifiers. Refer to the Design Features section for more information.
17
AGNDD
Ground Reference Pin for DAC D Output Amplifier.
18
VOUTD
Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 k, 200 pF load.
19
VOUTC
Analog Output Voltage of DAC C. Buffered output with a nominal full-scale output range of ±10 V. The output
amplifier is capable of directly driving a 10 k, 200 pF load.
20
AGNDC
Ground Reference Pin for DAC C Output Amplifier.
21
AGNDB
Ground Reference Pin for DAC B Output Amplifier.
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