參數(shù)資料
型號: AD5765CSUZ
廠商: Analog Devices Inc
文件頁數(shù): 11/28頁
文件大?。?/td> 0K
描述: IC DAC 16BIT QUAD 5V 1LSB 32TQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: AD5763/65 Metal Layer Edit Change 08/Sept/2009
設(shè)計資源: High Accuracy, Bipolar Voltage Output Digital-to-Analog Conversion Using AD5765 (CN0073)
標(biāo)準(zhǔn)包裝: 1
設(shè)置時間: 8µs
位數(shù): 16
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 雙 ±
功率耗散(最大): 76mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 32-TQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 托盤
輸出數(shù)目和類型: 4 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 784 (CN2011-ZH PDF)
Data Sheet
AD5765
Rev. C | Page 19 of 28
TRANSFER FUNCTION
Table 8 shows the ideal input-code-to-output-voltage rela-
tionship for the AD5765 for both offset binary and twos
complement data coding.
Table 8. Ideal Output Voltage to Input Code Relationship
Digital Input
Analog Output
Offset Binary Data Coding
MSB
LSB
VOUTx
1111
2 VREF × (32,767/32,768)
1000
0000
0001
2 VREF × (1/32,768)
1000
0000
0 V
0111
1111
2 VREF × (1/32,768)
0000
2 VREF × (32,767/32,768)
Twos Complement Data Coding
MSB
LSB
VOUTx
0111
1111
2 VREF × (32,767/32,768)
0000
0001
2 VREF × (1/32,768)
0000
0 V
1111
2 VREF × (1/32,768)
1000
2 VREF × (32,767/32,768)
The output voltage expression for the AD5765 is given by
×
+
×
=
536
,
65
4
2
D
V
REFIN
OUT
where:
D is the decimal equivalent of the code loaded to the DAC.
VREFIN is the reference voltage applied at the REFAB and
REFCD pins.
ASYNCHRONOUS CLEAR (CLR)
CLR is a negative edge triggered clear that allows the outputs to
be cleared to either 0 V (twos complement coding) or negative
full scale (offset binary coding). It is necessary to maintain CLR
low for a minimum amount of time (see Figure 2) for the
operation to complete. When the CLR signal is returned high,
the output remains at the cleared value until a new value is
programmed. If, at power-on, CLR is at 0 V, then all DAC
outputs are updated with the clear value. A clear can also be
initiated through software by writing the command 0x04XXXX
Table 9. AD5765 Input Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15:DB0
R/W
0
REG2
REG1
REG0
A2
A1
A0
Data
Table 10. Input Register Bit Functions
Bit
Description
R/W
Indicates a read from or a write to the addressed register
REG2, REG1, REG0
Used in association with the address bits to determine if a read or write operation is to the data register, offset
register, gain register, or function register
REG2
REG1
REG0
Function
0
Function register
0
1
0
Data register
0
1
Coarse gain register
1
0
Fine gain register
1
0
1
Offset register
A2, A1, A0
Used to decode the DAC channels
A2
A1
A0
Channel Address
0
DAC A
0
1
DAC B
0
1
0
DAC C
0
1
DAC D
1
0
All DACs
D15:D0
Data bits
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